SoC Appears to no longer fit inside Ice40 FPGA

[JamesTimothyMeech]

When I run: sudo ./icebreaker.py --debug --flash

I get this error which seems to imply that the SoC no longer fits inside the Ice40 using the latest versions of LiteX and Yosys: Info: Running main analytical placer, max placement attempts per cell = 3583164. ERROR: Failed to expand region (0, 0) |_> (25, 31) of 5311 ICESTORM_LCs 0 warnings, 1 error Traceback (most recent call last): File "./icebreaker.py", line 246, in <module> main() File "./icebreaker.py", line 236, in main builder.build() File "/home/meechy/Casino/icebreaker-litex-examples/soc/deps/litex/litex/soc/integration/builder.py", line 315, in build vns = self.soc.build(build_dir=self.gateware_dir, **kwargs) File "/home/meechy/Casino/icebreaker-litex-examples/soc/deps/litex/litex/soc/integration/soc.py", line 1131, in build return self.platform.build(self, *args, **kwargs) File "/home/meechy/Casino/icebreaker-litex-examples/soc/deps/litex/litex/build/lattice/platform.py", line 43, in build return self.toolchain.build(self, *args, **kwargs) File "/home/meechy/Casino/icebreaker-litex-examples/soc/deps/litex/litex/build/lattice/icestorm.py", line 207, in build _run_script(script) File "/home/meechy/Casino/icebreaker-litex-examples/soc/deps/litex/litex/build/lattice/icestorm.py", line 147, in _run_script raise OSError("Error occured during Yosys/Nextpnr's script execution.") OSError: Error occured during Yosys/Nextpnr's script execution.

[JamesTimothyMeech]

Here is the resource usage to help make my point: Info: Device utilisation: Info: ICESTORM_LC: 5312/ 5280 100% Info: ICESTORM_RAM: 13/ 30 43% Info: SB_IO: 16/ 96 16% Info: SB_GB: 8/ 8 100% Info: ICESTORM_PLL: 1/ 1 100% Info: SB_WARMBOOT: 0/ 1 0% Info: ICESTORM_DSP: 0/ 8 0% Info: ICESTORM_HFOSC: 0/ 1 0% Info: ICESTORM_LFOSC: 0/ 1 0% Info: SB_I2C: 0/ 2 0% Info: SB_SPI: 0/ 2 0% Info: IO_I3C: 0/ 2 0% Info: SB_LEDDA_IP: 0/ 1 0% Info: SB_RGBA_DRV: 0/ 1 0% Info: ICESTORM_SPRAM: 4/ 4 100%

[JamesTimothyMeech]

I'm using Yosys 0.28+6 (git sha1 cee3cb31b, clang 10.0.0-4ubuntu1 -fPIC -Os)

[Disasm]

I think it's a good idea to report this to LiteX

[JamesTimothyMeech]

Same issue with Yosys 0.30+1 (git sha1 5813809ad, clang 10.0.0-4ubuntu1 -fPIC -Os). I'll make an issue on LiteX

[JamesTimothyMeech]

Does anyone know a yosys and litex version for which the SoC fits in the Ice40?

[Disasm]

It builds on my machine if I update migen submodule. Yosys 0.10+12 (open-tool-forge build) (git sha1 356ec7bb, gcc 9.3.0-17ubuntu1~20.04 -Os)

[JamesTimothyMeech]

Thanks, I have run git checkout master in migen and then git pull to update it but it said that it is already up to date. I recently updated my litex installation and now I get this error when running the script : jamesmeech@Jamess-MacBook-Pro-10 soc % sudo ./icebreaker.py --debug --flash lxbuildenv: v2020.6.1.1 (run ./icebreaker.py --lx-help for help) Traceback (most recent call last): File "/Users/jamesmeech/Desktop/Casino/icebreaker-litex-examples/soc/./icebreaker.py", line 35, in <module> from litex_boards.platforms.icebreaker import Platform, break_off_pmod File "/Users/jamesmeech/Desktop/Casino/icebreaker-litex-examples/soc/deps/litex-boards/litex_boards/__init__.py", line 70, in <module> t = importlib.import_module(f"litex_boards.targets.{target}") ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ File "/usr/local/Cellar/python@3.11/3.11.3/Frameworks/Python.framework/Versions/3.11/lib/python3.11/importlib/__init__.py", line 126, in import_module return _bootstrap._gcd_import(name[level:], package, level) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ File "/Users/jamesmeech/Desktop/Casino/icebreaker-litex-examples/soc/deps/litex-boards/litex_boards/targets/numato_aller.py", line 28, in <module> from litepcie.phy.s7pciephy import S7PCIEPHY File "/Users/jamesmeech/Desktop/Casino/Enjoy_Digital/litepcie/litepcie/phy/s7pciephy.py", line 22, in <module> class S7PCIEPHY(LiteXModule): ^^^^^^^^^^^ NameError: name 'LiteXModule' is not defined

What have I broken here? I'm keen to fix it so I can try out your fix!

I have added the location of the litex install to my path as described here: https://github.com/enjoy-digital/litex/issues/1589

[Disasm]

This repository already includes compatible versions of dependencies. All you need is to clone this repository with all the submodules (git clone --recursive https://github.com/icebreaker-fpga/icebreaker-litex-examples). If you have python <=3.10 this should be good to go, for 3.11 you'll need to update the migen submodule (git submodule update --remote soc/deps/migen).

[JamesTimothyMeech]

Thanks so the problems are on my end. I'm unfortunately stuck trying to figure out why I have the NameError: name 'LiteXModule' is not defined error.

[JamesTimothyMeech]

Thanks both for you help, I am closing this issue based on the comment from Enjoy_Digital https://github.com/enjoy-digital/litex/issues/1707

[JamesTimothyMeech]

Is there any straightforward way I could use the makefile from c-riscv-blink with the SoC built by litex from:https://github.com/enjoy-digital/litex/issues/1707?

I have been trying to compile some code using the litex generated makefiles but I have been running into some errors that I can't fix: https://github.com/enjoy-digital/litex/issues/1704. I wanted to try out this repository because the examples and makefile are more simple and I though I would have more of a chance understanding it and building up the code and libraries I need for my program.

make prog seems to run successfully but I don't see any terminal printout using litex_term, screen, or wishbone_utils.

[Disasm]

You need to select some way of code execution first. AFAIK LiteX SoCs run BIOS from ROM and then it can chainload something from other storage devices, but you need to have one and also use the binary format LiteX uses. This implementation loads code directly from SPI flash skipping the BIOS part. It doesn't even build the BIOS code (builder_kwargs["compile_software"] = False).

[JamesTimothyMeech]

Thanks for the information! I'll go ahead and close the issue and make do with the litex tools. Getting this to work is probably beyond me right now