Closed rahulearn2019 closed 1 year ago
Can you give more info on how this is relevant to OpenFASOC, please? I see that you are using openroad flow scripts github repository.
On Sat, 22 Apr, 2023, 4:15 pm Rahul Tiwari, @.***> wrote:
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The design has a analog block whose GDS is generated using ALIGN and provided as dummy verilog to the flow. It has a mux as the digital block. OpenFASOC uses OpenROAD for RTL2GDS right? OpenROAD Flow takes a design from the IMC-gen/flow/design/ directory and runs it through its flow, generating a DEF and a GDS at the end. The design is specified by using the generated Verilog files and a config.mk file that configures OpenROAD Flow to the design
How are you using OpenFASOC for your analog block here? It would be helpful if you are more specific with OpenFASOC while explaining your problem.
Not sure if this is relevant anymore so closing it.
While trying to generate the gds, i am getting following error during global route stage It says route not created for one of the inputs to design and then says - "signal 11 received" PnR failed
5_1_fastroute.log