Open harshkhandeparkar opened 5 months ago
@harshkhandeparkar any plans to finish this PR?
@harshkhandeparkar any plans to finish this PR?
Juan was working on fixing the layout/LVS issues. Once they are fixed, this PR might be good to go.
is this ready for review @harshkhandeparkar
is this ready for review @harshkhandeparkar
Yes.
If DRC and LVS are passing, you'll need to uncomment the LDO job from the build and test workflow
Closes #264
Changes
LDO_COMPARATOR_LATCH
site to the double-height siteunithvdbl
provided by sky130hvl.PT_UNIT_CELL
site tounithv
fromunithd
, which is meant for sky130hd.VREG
voltage domain size by 1 micron on the x-axis on both sides. This prevents the core area rows from reaching the bottom (See Fig. 1 and Fig. 2)LDO_COMPARATOR_LATCH
placement position, which was wrong because of theMY
(mirror along y-axis) orientation.save_images.tcl
script. The upstream ORFS changes were incorporated (same as #256).trim
pin mismatch issueContext
Figure 1
Floorplan without increasing
VREG
domain size. Rows are colored in green.Figure 2
Floorplan after increasing
VREG
domain size. Rows, colored in green, do not extend to the bottom near the edges.Figure 3
Final output for array size =
129
(load current =10mA
) and placement density =0.6
.Figure 4
Final output for array size =
13
(load current =1mA
) and placement density =0.35
.Figure 5
Allowed (ie, with the placement converging) place densities, estimated placement density according to the current formula, and median allowed densities.