Glayout DRC and LVS in CI

[chetanyagoyal]

Implements the following changes -

1. Create a pythonic parser file that:
   • Writes the specified component's gds
   • Writes its netlist
   • Validates the DRC results by looking at the number of lines in the reports and the magic subprocess return codes
   • Validates the LVs results by parsing the report for exceptions and checks the magic (extraction) and netgen (LVS) subprocess return codes
2. Create a yaml workflow file to:
   • pull the stable docker image
   • run the parser file by specifying the component to run drc and lvs for
3. makes the antenna diodes optional in diff_pair_ibias_netlist to allow for NoneType being passed (when with_antenna_diodes=0 in opamp)
4. updates the diff_pair_ibias code to account for antenna diodes being passed as 0
5. Update the differential to single ended converter netlist
   • .subckt definition now matches the parameters being passed
   • this makes things the DIFF_TO_SIGLE netlist LVS clean
6. Switch around pin around in mimcap netlist reference in opamp gain stage
7. Update the current mirror netlist:
   • to use length as minimum transistor length if passed as None
   • pass length and width to the .subckt statements
8. General quality of life improvements in lvs, drc (magic and klayout) in mappedpdk
9. modify fet netlist:
   • to pass length, width, multipliers and fingers to .subckt calls
   • length is ltop
   • width is mtop
   • fingers * multipliers is mtop (the number of parallel devices)
   • multipliers is dummy multipliers
   • divide the number of main fet multipliers by two to fix the reported width from cdl always being double of whats in the extracted spice
10. add with_pins argument in generate_netlist to allow removal of top level's pins

[msaligane]

is this ready for review?

[d-m-bailey]

@msaligane the mappedpdk.py file contains the following extraction commands

select top cell
extract all
ext2spice lvs
ext2spice -o {str(lvsmag_path)}

load {design_name}
extract all
ext2spice lvs 
ext2spice rthresh 0
ext2spice cthresh 0
ext2spice -o {str(pex_path)}

load {design_name}
extract all
ext2spice cthresh 0
ext2spice -o {str(sim_path)}

I think the same extraction is happening 3 times. I don't think the ext2spice modify the extracted data (*.ext files), just how that information is netlisted.

The default extract option is to connect virtual nets (nets with the same name) that are not physically connected.

You might want to use the detailed parasitic resistance flow described here.

The netgen lvs command used is a one line command that should work for simple circuits. Multiple netlists and mixed signal designs require extra handling.

You might want to add a check for unexpected blackboxes. netgen will sometimes match an empty subckt to an actual layout or visa versa because it assumes that one or the other is a blackbox.

[chetanyagoyal]

Contributor

@d-m-bailey I addressed the repeated .ext extractions in this commit.

• Adding ext2resist didn't seem to make a difference in the report.
• From what I read in the documentation, adding -blackbox seemed like a good check to add

Thank you for the help!

[chetanyagoyal]

@msaligane this is ready to merge

[alibillalhammoud]

@srpathen @arldai can you take a look?