Instructions

[kazimergun]

''I will soon add instructions for building the SHD FPGA image, building the PC software, and actually getting the detector running on your bladeRF with the real-time visualization in MATLAB or Octave.''

Hi, can you share how to get it running with bladeRF ?

[ifrasch]

Hi, I haven't had the time to add instructions yet but will be working on it. You'll need to:

• Clone the original bladeRF repository, then copy over a bunch of files from the bladeRF-shd repo (I'll write a script to do this)
• Compile libbladeRF (the bladeRF PC software libraries)
• Download and Install Quartus (free) and compile the FPGA image
• Open Quartus, hook up the bladeRF device using the JTAG USB blaster cable ($50, required if you don't have a paid Quartus license), and load the FPGA
• Compile and run my program bladeRF-shd.c.
• Run plot_shd_output.m in Octave where you'll get a real-time visualization of the spectrum and detected holes

I'll put this all in some clear instructions.

[kazimergun]

Hi again, Why do we need JTAG USB blaster cable ? Isn't loading .rbf file enough using bladeRF-cli -l command ?

[ifrasch]

My design uses Altera's FFT IP core. Unfortunately, if you are using the free version of Quartus with no IP license, you will not be able to generate a .rbf file which can be loaded through the USB cable with bladeRF-cli. Instead, you need to use Altera's OpenCore Plus evaluation feature to load the FPGA, which requires the JTAG USB blaster cable (available at https://www.digikey.com/product-detail/en/terasic-inc/P0302/P0302-ND/2003484).

For this evaluation feature, a special time-limited .sof file will be generated and must be loaded onto the FPGA using the JTAG cable with Quartus open. You can either keep the cable attached after you program the FPGA, and the IP core will work without a time limit, or you can detach the cable and the IP core will work for a 1 hour.

If you plan on doing any additional FPGA development with the bladeRF or Intel/Altera FPGAs, the $50 cable is a good idea to own anyway. It allows you to debug your FPGA designs while they are running - you can probe FPGA signals with SignalTap or step through a Nios program line-by-line using the debugger.

[yannicklemoullec]

Dear Ian,

Two of my students (Tallinn University of Technology) are trying to build your project.

Right now we are stuck with the following error message while compiling the C code:
... src/shd_nios.c:2:32: fatal error: nios_pkt_shd_start.h: No such file or directory

Indeed, it looks as if this file is not included in your repository. Could you please add it?

Thank you!

[ifrasch]

@yannicklemoullec Yes, there's a mistake there. I had renamed that file to something else, but forgot to update the #include line in shd_nios.c - on line 2 it should be:

#include "nios_pkt_shd_control.h"

My bad. Somehow I never ran into that error, which is weird. Will update that soon. Sorry for the late response.

Edit: Added the fix.

[yannicklemoullec]

Dear Ian,

Thank you very much for sharing this fix, we will give it a try.

Seasons' greetings from Estonia, Yannick

On Dec 15, 2017 06:41, "Ian Frasch" notifications@github.com wrote:

@yannicklemoullec https://github.com/yannicklemoullec Yes, there's a mistake there. I had renamed that file to something else, but forgot to update the #include line in shd_nios.c - on line 2 it should be:

include "nios_pkt_shd_control.h"

My bad. Somehow I never ran into that error, which is weird. Will update that soon. Sorry for the late response.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub https://github.com/ifrasch/bladeRF-shd/issues/1#issuecomment-351912080, or mute the thread https://github.com/notifications/unsubscribe-auth/AFKM6cLpIJUhDbQlp-JPwj-IsYsTkpIVks5tAfiQgaJpZM4QKN2m .