This PR introduces the native implementation of V0 and V1, i.e. an implementation comprising only gates that can be physically realizable on Rigetti QPUs (see here and here).
Incidentally, since It turns out that we cannot alter the global phase of single-qubit operations, this PR removes global_phase_circuit and corresponding flags from other circuits that used it.
This PR introduces the native implementation of V0 and V1, i.e. an implementation comprising only gates that can be physically realizable on Rigetti QPUs (see here and here).
Incidentally, since It turns out that we cannot alter the global phase of single-qubit operations, this PR removes
global_phase_circuitand corresponding flags from other circuits that used it.