HALT input signal. - Githubissues

ijor / fx68k

FX68K 68000 cycle accurate SystemVerilog core

GNU General Public License v3.0

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Closed srg320 closed 4 years ago

srg320 commented 4 years ago

Will support for the HALT input signal and RESET/HALT signals combination be added?

jotego commented 4 years ago

I'd also like to see support for this.

srg320 commented 4 years ago

Logs of single-step mode HALT in sub cpu in real SegaCD. Maybe this information will help somehow.

dma_pcm dma_prgram

ijor commented 4 years ago

Thanks. It is helpful and it confirms the theory. Support for HALT single step coming soon ...

ijor commented 4 years ago

Commited support for HALT single step