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ijor / fx68k

FX68K 68000 cycle accurate SystemVerilog core
GNU General Public License v3.0
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X assignments #10

Closed jotego closed 2 years ago

jotego commented 2 years ago

Excuse my ignorance, but why do you assign an X to a register? Why have this in synthesizable logic?

https://github.com/ijor/fx68k/blob/0602ee4627b10f301298f2673d826cdd6baa9327/fx68k.sv#L1250

a1exh commented 2 years ago

X-propagation for simulation? I regularly assign things to X in non-synthesisable code, particularly defaults in sequential case statements to allow for x-propagation.

FPGA synthesis optimisation? Some tools understand assignment to X as don't care and thus don't infer latches.

There is a lint error here though as rxReg is 4-bit.

jotego commented 2 years ago

Yes, there are a number of width assignment errors like that one, probably unimportant. I could make a PR for them if Ijor is interested.