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ijor / fx68k

FX68K 68000 cycle accurate SystemVerilog core
GNU General Public License v3.0
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SystemVerilog to Verilog conversion seems to be successful #16

Open Willyarma opened 3 weeks ago

Willyarma commented 3 weeks ago

I attempted to convert this project to Verilog so I could use it in Xilinx ISE. I used a utility called sv2v (https://github.com/zachjs/sv2v). I had to change 3 wires to reg after conversion and then it synthesised OK.

The signals I had to change are in the ALU and are: subResult subCout subOv

Not tested thoroughly but it seems to be working and is running software and interrupts work.

a1exh commented 3 weeks ago

Bug in the conversion tool. Those signals were declared as logic in the original code which can be reg and wire.

Why not try using SymbiYosis to prove the two are identical formally?

zachjs commented 1 week ago

I identified the issue responsible for the conversion issue mentioned above. With https://github.com/zachjs/sv2v/commit/73a9cc6750d6896eb0c90a33cf56c971237e5374, subResult, subCout, and subOv are now correctly converted to reg rather than wire when I run sv2v fx68k/*.sv. Please let me know if you agree with the fix!

If you run into any other issues, please consider filing them over at https://github.com/zachjs/sv2v/issues. These bugs can be fixed! I'm glad I stumbled upon this discussion anyway and could benefit from your debugging effort. Thank you!

Willyarma commented 1 week ago

Thanks zachjs, thats amazing!

I wasn't complaining, I meant this post to be information to help others in my situation, I was really pleased with the outcome. I just couldn't figure out how to tag the post as info.