ijor / fx68k

FX68K 68000 cycle accurate SystemVerilog core
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Possible issue with UNLK #3

Closed apolkosnik closed 4 years ago

apolkosnik commented 4 years ago

Toni Wilen's cputest flags a possible issue with UNLK instruction.


CPUlvl=0, Mask=00ffffff Code=007c0000 SP=007ffbc0 ISP=00800000
 Low: 00000000-00008000 High: 00ff8000-01000000
Test: 00780000-00800000 Safe: ffffffff-ffffffff
UNLK.L:
data/68000/UNLK.L/0000.dat. 0...

8:  4e5f    unlk     sp
A7: expected f01f007c but got e993f600
Registers before:
D0: 00000010 D1: 00000000 D2: ffffffff D3: ffffff00
D4: ffff0000 D5: 80008080 D6: 7fff7fff D7: aaaaaaaa
A0: 00000000 A1: 00000080 A2: 00008000 A3: 00007fff
A4: fffffffe A5: ffffff00 A6: 007bff00 A7:*007ffbc0
SR: 0000   PC: 007c0000 ISP: 007fff80
T1=0 T0=0 S=0 M=0 X=0 N=0 Z=0 V=0 C=0
000   PC: 007c0000 ISP: 007fff80
T1=0 T0=0 S=0 M=0 X=0 N*0 Z!0 V*0 C=0

Registers after:
SR:*000e   PC: 007c0002 ISP: 007fff80
T1=0 T0=0 S=0 M=0 X=0 N*1 Z!1 V*1 C=0
OK: No exception generated
Registers after:
SR:*000e   PC: 007c0002 ISP: 007fff80
T1=0 T0=0 S=0 M=0 X=0 N*1 Z!1 V*1 C=0
OK: No exception generated
Registers after:
A4: fffffffe A5: ffffff00 A6: 007bff00 A7:*e993f600
SR: 0000   PC: 007c0002 ISP: 007fff80
T1=0 T0=0 S=0 M=0 X=0 N=0 Z=0 V=0 C=0
OK: No exception generated ```
a1exh commented 4 years ago

Toni Wilen replied "There is chance this report is bogus. I have seen same error sometimes but also UNLK SP test succeeding. Does it report same error if you only generate UNLK tests?"

Can you generation UNLK tests only and retry?

ijor commented 4 years ago

Seems a false positive error indeed. Thanks anyway for the testing and the report. I will close the issue