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ijor / fx68k

FX68K 68000 cycle accurate SystemVerilog core
GNU General Public License v3.0
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Add clock enable outputs for the E clock #5

Closed gyurco closed 3 years ago

gyurco commented 4 years ago

Sometimes it could be useful for 6800 friendly peripherals, like ACIA or VIA

jotego commented 4 years ago

These kind of signals do help to latch data correctly. I think it's a good idea to add them.

jotego commented 3 years ago

Isn't this already added? https://github.com/ijor/fx68k/blob/0602ee4627b10f301298f2673d826cdd6baa9327/fx68k.sv#L149

gyurco commented 3 years ago

Oh yes, it is.