ijor / fx68k

FX68K 68000 cycle accurate SystemVerilog core
GNU General Public License v3.0
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subq instruction bug #9

Closed jotego closed 3 years ago

jotego commented 3 years ago

The subq instruction in the code:

image

is not executed correctly by fx68k. Look at the following signal dump:

image

The CPU has to read the value in memory address $FFF310, decreased it by one and write it back. The value read is $8401, but the value written back is $0000 instead of $8400.

This is how the same instructions look like through the J68_CPU module, to serve as a reference:

image

You can see how the ram_data bus is decreased by one in this case.

Could you please look into this bug?

ijor commented 3 years ago

Jose,

You are performing a byte sized instruction. It is not $8401 - 1, it is $01 - 1. So the result is $00, and not $8400.

Also the FX68K behavior is correct. When performing a byte sized write, the byte data is replicated in the other half of the 16 bits data bus. That's what a real 68000 does and it is documented in Motorola hardware manual.

jotego commented 3 years ago

You're right. I'm back to square 1 then. I'll keep looking.