Open hayguen opened 3 years ago
The current code doesn't handle dynamic ADC sampling rate very well. Is there any benefit to the signal quality by doing so? Saving cpu is not a big problem as the machine with USB3.0 are reasonable powerful.
The use of a high sampling rate allows to gain in S/N in decimation, although I believe in the case the noise figure is determined by the R820T2 tuner. Using a lower sample rate in the ADC would require a low pass filter at the ADC input from R820T2 to eliminate aliasing. Now it's made by software IF filtering. The ability to vary the frequency of the ADC may in the future facilitate the use and adjustment of fixed crystal references for the ADC in other types of hardware similar to HF103.
probably i wasn't clear enough?: i am suggesting to add higher decimation factors (into r2c) leading to more and lower samplerates in HDSDR, e.g. 250 kSps, 500 kSps, 1 MSps, .. in addition to the 2, 4, 8, 16, 32 and 64 MSps.
probably, in addition, do not allow to select samplerates >= 32 MSps in VHF? but, not sure about this.
for 2 reasons:
reducing the ADC samplerate in VHF, e.g. from 64 MSps to 32 MSps is another totally independent topic. this might be interesting on some slower computers.
only able to down to 500k. I may need your help to debug what's wrong when have even lower sample rate. Check PR #156
When I only use the fixed EXTIO_LEN, i got audio lag. If I uses EXTIO_LEN < 512, i got frozen UI.
selecting lower samplerates in VHF should automatically reduce the R820T-tuners' IF bandwidth - to avoid oversteering of ADC