My design is a simple loopback axi_dma mm2s to axi_dma s2mm. On a xilinx zynqMP ultrascale+ zcu102.
I was wondering why only on a cold start (first run of userspace app is the RX buffer all zero)?
All sequential runs the RX buffer equals the TX buffer.
I tried a FIFO in btween the transaction, but got the same result.
Hi all,
My design is a simple loopback axi_dma mm2s to axi_dma s2mm. On a xilinx zynqMP ultrascale+ zcu102.
I was wondering why only on a cold start (first run of userspace app is the RX buffer all zero)? All sequential runs the RX buffer equals the TX buffer.
I tried a FIFO in btween the transaction, but got the same result.
thanks,