Closed ret closed 5 years ago
I spent all day yesterday working on debugging the problem. I rewrote the entirety of dummyusb. It's ~3% smaller now (and uses 200 fewer LUTs).
Naturally the problem was somewhere else.
The problem was due to skew between the 48 MHz and 12 MHz clock domains. We used to use a Clock Resource Generator (CRG) from the litex_boards
repository, but that got removed. Rather than fixing it upstream, I added a CRG to workshop.py
and workshop_rgb.py
. We'll get that change pushed upstream, but for now we'll keep the local copy of the CRG within the workshop files.
If you update litex-workshop
it should work now. If you then do a git submodule sync
, you should get the new USB core that's 200 LCs smaller.
Wow! Thanks a ton, Sean! Will rerun my experiment and close this issue later today.
In the
litex/workshop.py
andlitex/workshop_rgb.py
examples, I often have to retry reads and writes via thewishbone-tool
to work aroundBridgeError(USBError(Pipe))
. This is happening on box Linux and OSX for me.Have others experienced similar reliability challanges?