Tracking issue for gates

[NogginBops]

This is a tracking issue for gates and their implementation status:

This includes both simulation implementation as well as visual implementation. If a component requires it's own discussion that issue will be linked next to the component in this list.

Prio 1:

• [x] Constant
• [x] Input/output pins
• [x] Buffer
• [x] Not gate
• [x] And gate
• [x] Nand gate
• [x] Or gate
• [x] Nor gate
• [x] Xor gate
• [x] Xnor gate
• [x] Tri-state buffer
• [x] Tri-state inverter
• [x] D/T/JK/SR Flip Flop
• [x] Probe
• [x] Clock
• [x] LED
• [x] Button

Prio 2:

• [ ] Register
• [ ] Shift register
• [ ] Counter
• [ ] Imply gate
• [ ] Nimply gate

Prio 3:

• [ ] Mux
• [ ] DeMux
• [ ] ROM
• [ ] RAM
• [ ] Splitter
• [ ] User-defined components
• [ ] Tunnel