Closed mooinglemur closed 10 months ago
Looks good. Thanks!
Oh, I see this is a draft. Let me know when you think this is ready to pull.
That it affects bitmap mode is merely a side effect of the Verilog since that code is common to both there.
I plan to keep it as a draft until the Verilog is merged. Thanks :)
This change mirrors that of https://github.com/X16Community/x16-emulator/pull/197 and is an emulated implementation of this change https://github.com/X16Community/vera-module/pull/23