infiniteorbits / hart-software-services

PolarFire SoC hart software services
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Update HSS to latest version #4

Open tiwari3101 opened 3 months ago

tiwari3101 commented 3 months ago

When the latest version of the HSS is used on the EM/FM, the DDR training passes but the software payload does not boot.

tiwari3101 commented 3 months ago

Tested the latest HSS (v2024.02.1) on the Icicle Kit with a payload compiled from the main (commit e78cb493bf0e1bf279e49fdca0b3dcf65fe4ffd4). The yaml file used is from the older version of hss. (v0.99.33). The payload boots successfully.

A new payload was uploaded to sector 0 using CSP and on rebooting, the new payload boots successfully as well.

There was an error noted in the HSS that does not yet affect the software:

Image

tiwari3101 commented 2 months ago

Able to boot the software on the EM003. There are some 'errors' observed in the HSS output on UART0.

Image

Meeting with Microchip on 15/07 confirmed that the logs were normal (both on the Icicle Kit and the EM003). This will be fixed in future releases.

Issue:

tiwari3101 commented 2 months ago

Parallel investigation regarding the slow DDR Training on all EMs with all versions of HSS. Performed tests as recommended by Microchip, logs attached below:

mpfs-mmuart-interrupt.txt mpfs-hal-ddr-demo.txt

Comments by Microchip:

tiwari3101 commented 2 months ago

All the issues with the HSS as of date are documented here: https://docs.google.com/document/d/1o13Kvx4mcxVh3mEmBoWlDEgqCyaWU-ll3IJoYu3bFrg/edit?usp=sharing

mannykoum commented 2 months ago

Any updates on this?

abelixrev commented 2 months ago

I have updated the master branch with the HSS v2024.06 version from July 3rd, commit 88771e7729fb8cc05e6c0a12195ebb29028ae4d6.

I have created a branch from master and added the slot_selection feature: HSS/v0.99.41-slot-selection.

I have resolved the issue where sometimes the HSS loads the payload and boots the software, but the software doesn't start. To fix this, I modified services/mmc/mmc_api.c to ensure the eMMC always initializes with a clk_rate of 50MHz and in SDR mode (previously it was 200MHz and in HS200 mode).

Due to the previous change, the HSS has also been prevented from rebooting itself and performing the DDR training multiple times before booting the software.

In this version, some 'errors' observed in the HSS output on UART0 do not appear (it seems Microchip has resolved this in this version).

This version has been validated on EM002 and EM003 and works correctly.

Therefore, we can conclude that we have an updated HSS version that works with slot selection. The only remaining issue seems to be the time taken for DDR training.