ILA cannot scan the correct signal with BRAM parallel ports

ing0331 / FPGA

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Open ing0331 opened 1 year ago

ing0331 commented 1 year ago

方法1: Block design中，手動在ILA、BRAM拉訊號線(避免空接線) 方法2: 將ILA掃描頻率接50MHz(Zynq設定檔)(請確保Debug Hub 時鐘頻率至少是JTAG 時鐘頻率的2.5 倍)

ing0331 commented 11 months ago

ans: 應以enb為trigger