IOSim's MVars

[coot]

MVar's for IOSim

[bolt12]

Also stylish is failing in CI

[coot]

I don't think I will change my PR to use MVars

You're using the io-sim TVar's there, isn't it? The advantage of these MVar's is that they are provide fairness, unlike TMVar's.

btw, this implementation relies on @dcoutts idea.

[bolt12]

You're using the io-sim TVar's there, isn't it? The advantage of these MVar's is that they are provide fairness, unlike TMVar's.

btw, this implementation relies on @dcoutts idea.

I was, now it is using STRef's. How does STM provide fairness, I remember seeing that STM doesn't exactly guarantee fairness like MVars do

[coot]

How does STM provide fairness, I remember seeing that STM doesn't exactly guarantee fairness like MVars do

STM doesn't provide fairness, that's why the dance with MVarState and both putMVar and takeMVar are not implemented using a single atomic STM action.

[bolt12]

STM doesn't provide fairness, that's why the dance with MVarState and both putMVar and takeMVar are not implemented using a single atomic STM action.

So when you say:

Including a default implementation using 'MonadSTM', which guarantees fairness.

what do you mean by fairness? what I understand by fairness here is that if you have various thread blocked on waiting for a take in a loop, and one thread putting in the MVar in a loop, eventually all threads will be able to acquire the take. I do not think STM guarantees this fairness

[coot]

what do you mean by fairness?

It means blocked putMVars (or takeMVars) are served in FIFO order. STM indeed does not guarantee that, and that's why putMVar and takeMVar are more complex than what TMVar would provide, also note that we need two atomically blocks not a single one! Does this explains it well?

[coot]

The same fairness (FIFO order) is guaranteed by MVar's provided by base: ref.

[bolt12]

@coot I understand now! Thank you! :D