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insane-adding-machines / unicore-mx

UniCore-MX | Universal Core for ARM Cortex-M0/0+/3/4/7/X
GNU General Public License v3.0
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STM32 Family USB OTG FS/HS have varying number of endpoints #68

Open kuldeepdhaka opened 6 years ago

kuldeepdhaka commented 6 years ago 
STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
        dedicated RAM of 1.25[FS] Kbytes

        Up to 8[FS] host channels (pipes)

        1 bidirectional control endpoint0
        3[FS] IN endpoints
        3[FS] OUT endpoints
F105
F107

STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx
        dedicated RAM of 1.25[FS] / 4[HS] Kbytes

        Up to 8[FS] / 12[HS] host channels (pipes)

        1 bidirectional control endpoint0
        3[FS] / 5[HS] IN endpoints
        3[FS] / 5[HS] OUT endpoints
F205
F207
F215
F217

STM32F40xxx, STM32F41xxx, STM32F42xxx, STM32F43xxx
        dedicated RAM of 1.25[FS] / 4[HS] Kbytes

        Up to 8[FS] / 12[HS] host channels (pipes)

        1 bidirectional control endpoint 0
        3[FS] / 5[HS] IN endpoints
        3[FS] / 5[HS] OUT endpoints
F401
F405
F407
F411
F412
F412
F413
F415
F417
F423
F427
F429
F429
F437
F439

STM32F446xx
        dedicated RAM of 1.25[FS] / 4[HS] Kbytes

        Up to 12[FS] / 16[HS] host channels (pipes)

        1 bidirectional control endpoint0
        5[FS] / 7[HS] IN endpoints
        5[FS] / 7[HS] OUT endpoints
F446

STM32F469xx and STM32F479xx
        dedicated RAM of 1.25[FS] / 4[HS] Kbytes

        Up to 12[FS] / 16[HS] host channels (pipes)

        1 bidirectional control endpoint0
        5[FS] / 8[HS] IN endpoints
        5[FS] / 8[HS] OUT endpoints
F469
F469
F479

STM32F72xxx and STM32F73xxx
        dedicated RAM of 1.25[FS] / 4[HS] Kbytes

        Up to 12[FS] / 16[HS] host channels (pipes)

        1 bidirectional control endpoint0
        5[FS] / 8[HS] IN endpoints
        5[FS] / 8[HS] OUT endpoints
F722
F723
F732
F733

STM32F75xxx and STM32F74xxx
        dedicated RAM of 1.25[FS] / 4[HS] Kbytes

        Up to 12[FS] / 16[HS] host channels (pipes)

        1 bidirectional control endpoint0
        5[FS] / 8[HS] IN endpoints
        5[FS] / 8[HS] OUT endpoints
F745
F745
F746
F746
F756

STM32F76xxx and STM32F77xxx
        dedicated RAM of 1.25[FS] / 4[HS] Kbytes

        Up to 12[FS] / 16[HS] host channels (pipes)

        1 bidirectional control endpoint0
        5[FS] / 8[HS] IN endpoints
        5[FS] / 8[HS] OUT endpoints
F765
F767
F769
F777
F779

STM32H7x3
        dedicated RAM of 4 [HS] Kbytes

        Up to 16 [HS] host channels (pipes)

        1 bidirectional control endpoint0
        8[HS] IN endpoints
        8[HS] OUT endpoints
H743
H753

STM32L4x5 and STM32L4x6
        dedicated RAM of 1.25 [FS] Kbytes

        Up to 12 [FS] host channels (pipes)

        1 bidirectional control endpoint0
        5[FS] IN endpoints
        5[FS] OUT endpoints
L475
L476
L476
L486
L486
L496
L4A6
L4A6

In code, we need to consider the varying number of endpoints count.

DEVICE: Currently the values in code (endpoints including ep0) are hard coded to 6[FS] / 9 [HS] These values fit most target, but some target have different numbers.

HOST: Currently the values in code are hard coded to 8[FS] / 12 [HS] These values fit most target, but some target have different numbers.

Reference: https://github.com/libopencm3/libopencm3/issues/811

Note: Data based on all STM32 microcontrollers family datasheet with USB OTG FS/HS produced by ST (1 August 2017)

Note: Added Host mode data too.

kuldeepdhaka commented 6 years ago

Conclusion

    f1: dev=3[fs] , host=8[fs]

    f2: dev=3[fs]/5[hs], host=8[fs]/12[hs]

    f4:
        F446: dev=5[fs]/7[hs], host=12[fs]/16[hs]
        F469 / F469 / F479: dev=5[fs]/8[hs], host=12[fs]/16[hs]
        else: dev=3[fs]/5[hs], host=8[fs]/12[hs]

    f7: dev=5[fs]/8[hs], host=12[fs]/16[hs]

    h7: dev=8[hs], host=16[hs]

    l4: dev=5[fs], host=12[fs]

Note: dev do not include ep0