Closed JoeZiminski closed 6 months ago
Having read around a little more, I see the 32 channel blocks are multiplexed, with the 12 blocks sequentially processed across one sample, for the expected delay 1/12 a sample. If feedback on the companion article is useful, I would suggest amending the line 'Within each block, the 32 channels are sampled sequentially over a duration of one sample; therefore, there is a small lag of 1/12th of a sample between consecutive channels' (unless I have misunderstood something here).
Thanks, Joe
Thank you for your work on this well-documented and detailed pipeline.
I had a quick question to check my understanding on the section 'Sample shift' of the companion paper. The ADC operates on blocks of 32 channels, processing each channel sequentially over the period of one sample. There are 12 ADC blocks, in total covering 384 channels. I understood this as 12 ADC were operating in parallel, and so each channel (within a block) would be delayed 1/32 of a sample. Channels at the boundary between blocks would be delayed by an entire sample. However, the delay is 1/12th of a sample so my conceptualisation must be wrong.
If someone could explain in a little more detail this sample shift it would be much appreciated, thanks!
Joe