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integralfx / DDR4XMPEditor

Editor for DDR4 SPD and XMP
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Does setting the 'value' timings on the left do anything ? #30

Closed Panjaksli closed 4 months ago

Panjaksli commented 4 months ago

For example is there any difference between 'full' CL 19 with value of 95 and CL 19 with value 91 ? I'm tinkering with this, because CL18 doesn't boot, but CL 19 does, even when I lower it just one step above CL 18. Didn't see any improvement in latency, nor stability issues though. My thinking is, that commands can only be dispatched on each clock cycle, so how would the timing work otherwise no ?

integralfx commented 4 months ago

I'm not sure what you mean by 'full' CL 19 with value of 95 and CL 19 with value 91

Can you post a screenshot?

Panjaksli commented 4 months ago

image

I've studied how SPD info is stored in the meanwhile. The left value is apparently in multiples of MTB, which is fixed to 0.125 ns. So my guess is the CPU sets its own timings according to the time * frequency, rounded to nearest (larger) number of cycles ?

integralfx commented 4 months ago

Yes, that's correct

Time (ns) = Value * MTB + Offset, where MTB is 0.125 ns

Ticks = Frequency (ns) / Time (ns), rounded up to the nearest whole number

Panjaksli commented 4 months ago

Okay, pretty much solved, hope it helps other people looking for the same stuff.