Moving tWR to the end is not a good idea

[IslamGhunym]

Lower tWR have the potential to allow lower tRTP to be stable. Lower tRTP however means you can go lower on tRAS and probably be stable there which is one of the major timings. It is certainly a bad idea to move tWR to the end.

However tritary timings are not necessarily the one that should be left to end. an example is tRDWR and tCWL. While tRDWR is a tritary timing, tCWL is a secondary one. It is always better to have tRDWR not higher than 8 then tighten tCWL later for both stability and performance on Ryzen IMC.

[Agade09]

I have experienced this on my system. I could not get tRTP below 12, but after getting tWR to 10 I now seem stable at tRTP 5. One idea would be to add a step or add a note to recheck tRTP (then tRAS, then tRC?). I have read tRTP=tWR/2 elsewhere, which, for what it's worth, holds true on my system.

[IslamGhunym]

Still it certainly takes a lot of time to verify the stability when tWR is tightened and may lead to a lot of time waste if the user doesn't have enough experience and rushed through tWR to other timings, but for that we can simply add a note for extensive test when tightening tWR, but not pushing it to the end

[LunarPSD]

Lower tWR have the potential to allow lower tRTP to be stable.

Hi, do you mind linking a source or providing an example with stability tests used along with the amount of time the test(s) were run for, if applicable? It's been moved to the end by popular demand because errors caused by tWR are often intermittent and is a timing that most skip or save for last.

[LunarPSD]

I could not get tRTP below 12, but after getting tWR to 10 I now seem stable at tRTP 5... I have read tRTP=tWR/2 elsewhere, which, for what it's worth, holds true on my system.

I have heard the same about tRTP and tWR. When you could not get tRTP below 12, was the relationship between tWR and tRTP tRTP=tWR/2?

[IslamGhunym]

Lower tWR have the potential to allow lower tRTP to be stable.

Hi, do you mind linking a source or providing an example with stability tests used along with the amount of time the test(s) were run for, if applicable?

sure, I will try

[Agade09]

I could not get tRTP below 12, but after getting tWR to 10 I now seem stable at tRTP 5... I have read tRTP=tWR/2 elsewhere, which, for what it's worth, holds true on my system.

I have heard the same about tRTP and tWR. When you could not get tRTP below 12, was the relationship between tWR and tRTP tRTP=tWR/2?

No, not exactly, my motherboard defaulted tWR to 26 so 12 was not quite tWR/2 in that case.

[IslamGhunym]

No, not exactly, my motherboard defaulted tWR to 26 so 12 was not quite tWR/2 in that case.

It should be 13, but you certainly have Geardown mode enabled which means these timings can only be even so 12 not 13

The last time I did memory OC on Ryzen (Zen and Zen+) was stable on tWR=14 clks (1735 MHz) while tRTP was stable at 7 clks and there was errors bellow 7. The previous time I had similar experience too (tWR=20 stable and tRTP=10 stable and had some rare errors with tRTP=9 clks)

I never heard of the rule tRTP should be half tWR, but what I experienced confirms that. I still don't think of it as rule, but when you are tightening tRTP after tWR, the tRTP=tWR/2 is a good starting point try -1 from there and move up until you are fully stable.

[IslamGhunym]

Lower tWR have the potential to allow lower tRTP to be stable.

Hi, do you mind linking a source or providing an example with stability tests used along with the amount of time the test(s) were run for, if applicable? It's been moved to the end by popular demand because errors caused by tWR are often intermittent and is a timing that most skip or save for last.

Here is what you asked for: https://ibb.co/grjH1Nw https://ibb.co/nwkChDv

Here is an example of a Zen+ Overclocked to IMC limit. the CPU was running at about 3.88 GHz during the test on current thermal solution. (can go up to 4.2 GHz on 3D applications only) In the First image as shown tWR was 14 and tRTP was stable at 7 with 10 cycles of Extreme anta configurations over 6 hours In the second image tWR was loosened to 17 and tRTP was still on 7 showing 2 errors fast after 12 minutes of the same test. However loosening tWR to 18 will cause a BSOD error during OS booting up. On these particular samples tRAS was always stable even if it was set as low as 8 because the actual tRAS can't be lower than tRTP + tRCD(RD) which is 25 here so if I was have to increase tRTP to 13 to become stable without tightening tWR I will end up with much higher tRAS. tRAS however was loosened to 56 before tightening both tWR and tRTP so that it won't effect lowest tRTP I could set.

[integralfx]

Reverted in https://github.com/integralfx/MemTestHelper/commit/9ab5b5430d1cb4cc23d12f34b95f2c5194a49ce1