Merge "trying higher frequencies" section

[HarrySIsNotAvailable]

1. I have added a table for recommended timings for each frequency range by Eden. 16-20-20-40 (tCL-tRCD-tRP-tRAS) and tCWL=16 is very limiting in terms of the highest frequency achievable, I was only able to reach 3600 MT/s with these timings but after loosening to 20-24-24-48 and tCWL=20, I was able to hit 3800 MT/s.

2. The reason I have merged the "trying higher frequencies" section is that it is obsolete. You can simply do this in the first step while raising voltages and loosening timings as the frequency is raised with CR2 or GDM. The last step in here is getting CR1 or GDM disabled so why not do them set 2T and GDM enabled in the first place?

3. Instead of the 1.4v and 1.45 DRAM voltage suggestion, I have simply added a link to the recommended voltages section, otherwise there is no point of that existing. Same with IMC related voltages.

[davthenub]

Not that I disagree with you, I just feel like just one anecdotal example isn't a great reason to modify a guide that so many people use; instead actually explaining possible reasons might be a better way of justifying the change, so here goes:

If people started with 16-20-20-40 and had ICs that required much above 10ns tRCD (which is fairly common, as sub 10ns is generally more the exception than the rule), they'd be limited to below DDR4-4000. Not much of a problem for chiplet Ryzens, but on literally any other platform that's not really an acceptable loss, especially when the ICs might be perfectly capable of significantly higher frequency (example: unbinned 8 Gib DJR, or 16 Gib rev B) and going higher in frequency only costs...nothing really, other than typing in a slightly larger number. And for what? Those timings are going to be re-tightened later anyways, so 16-20-20-40 isn't really "loose" enough for finding max frequency. If you're gonna go loose enough to make sure the timings aren't limiting you, you'd better be sure they aren't in the way. It almost feels like this guide was written specifically for decently binned 8Gib B die, which is of course, not what most people are running...

[davthenub]

Sup!

Sorry, I have no idea how to use github and was like halfway through writing stuff, so sorry if none of it really makes sense. If i accidentally spammed a bunch of PRs to the actual guide can you remove them lol

On Fri, Dec 1, 2023 at 3:27 PM integralfx @.***> wrote:

@.**** requested changes on this pull request.

Looks good

May also be worth considering adding a step on when to increase IMC voltages or possibly adding a column for the IMC voltages in the table you added at step 5

In DDR4 OC Guide.md https://github.com/integralfx/MemTestHelper/pull/72#discussion_r1412658505 :

-4. Set primary timings to 16-20-20-40 (tCL-tRCD-tRP-tRAS) and tCWL to 16.

• • Most ICs need loose tRCD and/or tRP, so I recommend 20. +5. Set loose primary timings. See the table below.
• |Frequency|tCL|tRCD|tRP|tRAS|tCWL|
• |---|---|---|---|---|---|
• |<=3200|16|20|20|40|16|
• |3201-3600|18|22|22|44|18|
• |3601-4000|20|24|24|48|20|
• |4001-4400|22|26|26|52|22|
• |4400+|24|28|28|56|24|
• • Some ICs may not boot with very loose primary timings to begin with so it is recommended to loosen timings before the frequency range is met while increasing the frequency in the next step as detailed in the table above.

This sentence is a bit confusing

What do you mean by "before the frequency range is met"?

I'd suggest splitting this sentence into 2 to make it easier to read

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[HarrySIsNotAvailable]

Hi, sorry for the late reply I did not see that you had reviewed my PR.

• I have clarified the loosening timings as frequency is increased concept.

• I have also removed the suggestion to set FCLK to 1600mhz if the user is unsure what is stable because the reader should be stressing FCLK with P95 + OCCT VRAM as the frequency is increased so they will absolutely know what is stable. This might even confuse readers as it is suggested to keep FCLK, MCLK, UCLK the same several timings throughout the document, then it is suggested to randomly set it to 1600mhz.

• tCCDL does exist on some Asus UEFIs. It would be best for the user to find this timing manually, if they can't, then it should be quite obvious that it is not available.

Looks good

May also be worth considering adding a step on when to increase IMC voltages or possibly adding a column for the IMC voltages in the table you added at step 5

I have clarified this in this commit: Clarify increasing voltages. I don't really think it is appropriate to have voltage suggestion for a given frequency range as every chip is different. Maybe adding a suggestion to increment by 25mv from the recommended starting voltages is a better alternative?

[HarrySIsNotAvailable]

IMC section mentions that VCCIO should be 50mv lower than VCCSA but 1.15v is suggested for both. I've changed it from:

1.15v SA/IO to 1.2v SA and 1.15v IO which better aligns with the 50mv difference suggestion.