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intel / CacheLib

Pluggable in-process caching engine to build and scale high performance services
https://www.cachelib.org
Apache License 2.0
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NUMA bindings support for private memory #82

Closed vinser52 closed 1 year ago

vinser52 commented 1 year ago

I think we can merge these changes to our develop branch while we are waiting for PR95 to be upstreamed.

This change is Reviewable

byrnedj commented 1 year ago

Thank you for the PR.

Do you think you could add in the forcePageAllocation method from PosixShmSegment.cpp, so that each page is prefaulted? See https://github.com/intel/CacheLib/blob/main/cachelib/shm/PosixShmSegment.cpp#L350.

This reduces the number of minor page faults dramatically (from over 1.7M down to ~100K).

vinser52 commented 1 year ago

Do you think you could add in the forcePageAllocation method from PosixShmSegment.cpp, so that each page is prefaulted? See https://github.com/intel/CacheLib/blob/main/cachelib/shm/PosixShmSegment.cpp#L350.

I think PR #81 should help in that case.