DSA cache control bit is not flush operation specific

intel / DML

Intel® Data Mover Library (Intel® DML)

https://intel.github.io/DML/

MIT License

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DSA cache control bit is not flush operation specific #16

Closed lplewa closed 10 months ago

lplewa commented 2 years ago

Please update comments, or define cache-control flags for other operations.

https://github.com/intel/DML/blob/2050879cc9aa35e0c6354517736b66e475a4e124/include/dml/dmldefs.h#L133

abdelrahim-hentabli commented 1 year ago

Hey @lplewa, with the most recent updates to dml with moving DML_FLAG_PREFETCH_CACHE, which is the DML defined cache-control flag, to be a shared flag.

And for DML_FLAG_DONT_INVALIDATE_CACHE, which is a use of the same value as cache-control, but is used in a different way exclusively for the cache flush operation, it remains a cache flush specific flag.

Does this solve your issue?

mzhukova commented 10 months ago

Closing as the issue was addressed, but no response for a few months. Please, feel free to re-open if necessary.