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Timing violation in example - streaming_dma_afu #17

Open sneharaogr opened 4 years ago

sneharaogr commented 4 years ago

I have been working on compiling the streaming_dma_afu example on the FPGA devcloud using the Stratix 10 (D5005 PAC card) Devstack version 2.0.1. On compiling the design, I get timing-violations as given in the Output section of this query. Could anyone please suggest what the issue might be? I was not expecting the violations to exist in the standard example. I'm following the instructions given in the link here.

Environment:

Output Section: 

1) Taken from clocks.sta.fail.summary

Type  : 2_slow_900mv_100c setup 'mem|mem_bank[1].emif_ddr4_inst|emif_s10_0_core_usr_clk'
Slack : -0.249
TNS   : -5.320

Type  : 2_slow_900mv_100c setup 'u0|dcp_iopll|dcp_iopll_clk2x'
Slack : -0.180
TNS   : -11.450

Type  : 2_slow_900mv_0c setup 'mem|mem_bank[1].emif_ddr4_inst|emif_s10_0_core_usr_clk'
Slack : -0.067
TNS   : -0.204

Type  : MIN_fast_900mv_100c setup 'mem|mem_bank[1].emif_ddr4_inst|emif_s10_0_core_usr_clk'
Slack : -0.029
TNS   : -0.045

2) This is the first failing path's details taken from afu_default_2_slow_900mv_0c_setup.rpt file.

Path #1: Setup slack is -0.067 (VIOLATED)
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Path Summary                                                                                                                                          ;
+--------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property           ; Value                                                                                                                            ;
+--------------------+----------------------------------------------------------------------------------------------------------------------------------+
; From Node          ; fpga_top|inst_green_bs|ccip_std_afu|afu_inst|the_streaming_dma_test_system|emif_b_bridge|emif_b_bridge|cmd_fifo|out_payload[203] ;
; To Node            ; fpga_top|inst_green_bs|lm_pipe[1].local_mem_avmm_bridge|ddr_avmm_bridge|cmd_writedata[1][138]                                    ;
; Launch Clock       ; mem|mem_bank[1].emif_ddr4_inst|emif_s10_0_core_usr_clk                                                                           ;
; Latch Clock        ; mem|mem_bank[1].emif_ddr4_inst|emif_s10_0_core_usr_clk                                                                           ;
; Data Arrival Time  ; 6.372                                                                                                                            ;
; Data Required Time ; 6.305                                                                                                                            ;
; Slack              ; -0.067 (VIOLATED)                                                                                                                ;
+--------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------+
; Statistics                                                                              ;
+---------------------------+--------+-------+-------------+------------+--------+--------+
; Property                  ; Value  ; Count ; Total Delay ; % of Total ; Min    ; Max    ;
+---------------------------+--------+-------+-------------+------------+--------+--------+
; Setup Relationship        ; 3.336  ;       ;             ;            ;        ;        ;
; Clock Skew                ; -0.435 ;       ;             ;            ;        ;        ;
; Data Delay                ; 3.069  ;       ;             ;            ;        ;        ;
; Number of Logic Levels    ;        ; 1     ;             ;            ;        ;        ;
; Physical Delays           ;        ;       ;             ;            ;        ;        ;
;  Arrival Path             ;        ;       ;             ;            ;        ;        ;
;   Clock                   ;        ;       ;             ;            ;        ;        ;
;    Clock Network (Lumped) ;        ; 1     ; 3.199       ; 100        ; 3.199  ; 3.199  ;
;   Data                    ;        ;       ;             ;            ;        ;        ;
;    IC                     ;        ; 1     ; -0.001      ; 0          ; -0.001 ; -0.001 ;
;    Cell                   ;        ; 3     ; 0.078       ; 3          ; 0.000  ; 0.078  ;
;    uTco                   ;        ; 1     ; 0.402       ; 13         ; 0.402  ; 0.402  ;
;    Routing Element        ;        ; 24    ; 2.590       ; 84         ; 0.000  ; 0.211  ;
;  Required Path            ;        ;       ;             ;            ;        ;        ;
;   Clock                   ;        ;       ;             ;            ;        ;        ;
;    Clock Network (Lumped) ;        ; 1     ; 2.131       ; 100        ; 2.131  ; 2.131  ;
+---------------------------+--------+-------+-------------+------------+--------+--------+
Note: Negative delays are omitted from totals when calculating percentages

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Data Arrival Path                                                                                                                                                                                                                                                                                                 ;
+---------+----------+----+------+--------+--------------------------------------------+-----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Total   ; Incr     ; RF ; Type ; Fanout ; Location                                   ; Element Type                ; Element                                                                                                                                                                                      ;
+---------+----------+----+------+--------+--------------------------------------------+-----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 0.104   ; 0.104    ;    ;      ;        ;                                            ;                             ; launch edge time                                                                                                                                                                             ;
; 3.303   ; 3.199    ;    ;      ;        ;                                            ;                             ; clock path                                                                                                                                                                                   ;
;   3.303 ;   3.199  ; R  ;      ;        ;                                            ;                             ; clock network delay                                                                                                                                                                          ;
;   3.303 ;   0.000  ;    ;      ; 1      ; EC_X66_Y261_N21                            ; EC                          ; fpga_top|inst_green_bs|ccip_std_afu|afu_inst|the_streaming_dma_test_system|emif_b_bridge|emif_b_bridge|cmd_fifo|out_payload[203]                                                             ;
; 6.372   ; 3.069    ;    ;      ;        ;                                            ;                             ; data path                                                                                                                                                                                    ;
;   3.705 ;   0.402  ; RR ; uTco ; 2      ; EC_X66_Y261_N21                            ; EC                          ; fpga_top|inst_green_bs|ccip_std_afu|afu_inst|the_streaming_dma_test_system|emif_b_bridge|emif_b_bridge|cmd_fifo|mem_rtl_0|auto_generated|altera_syncram_impl1|ram_block2a202|portbdataout[0] ;
;   3.705 ;   0.000  ; RR ; RE   ; 1      ; EC_X66_Y261_N21                            ; EC                          ; EC                                                                                                                                                                                           ;
;   3.708 ;   0.003  ; RR ; RE   ; 1      ; MEDIUM_EAB_RE_X66_Y261_N0_I111             ; MEDIUM_EAB_RE               ; MEDIUM_EAB_RE                                                                                                                                                                                ;
;   3.897 ;   0.189  ; RR ; RE   ; 1      ; R10_X66_Y261_N0_I19                        ; R10 interconnect            ; H10                                                                                                                                                                                          ;
;   4.005 ;   0.108  ; RR ; RE   ; 1      ; C2_X75_Y259_N0_I30                         ; C2 interconnect             ; V2                                                                                                                                                                                           ;
;   4.140 ;   0.135  ; RR ; RE   ; 1      ; R4_X72_Y260_N0_I53                         ; R4 interconnect             ; H4                                                                                                                                                                                           ;
;   4.140 ;   0.000  ; RR ; RE   ; 1      ; R24_C16_INTERCONNECT_DRIVER_X71_Y260_N0_I0 ; R24/C16 interconnect driver ; WIRE_MUX                                                                                                                                                                                     ;
;   4.351 ;   0.211  ; RR ; RE   ; 1      ; C16_X71_Y260_N0_I26                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   4.519 ;   0.168  ; RR ; RE   ; 1      ; C16_X71_Y276_N0_I27                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   4.676 ;   0.157  ; RR ; RE   ; 1      ; C16_X71_Y292_N0_I26                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   4.815 ;   0.139  ; RR ; RE   ; 1      ; C16_X71_Y308_N0_I26                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   4.911 ;   0.096  ; RR ; RE   ; 1      ; R4_X72_Y324_N0_I16                         ; R4 interconnect             ; H4                                                                                                                                                                                           ;
;   5.007 ;   0.096  ; RR ; RE   ; 1      ; C2_X75_Y324_N0_I25                         ; C2 interconnect             ; V2                                                                                                                                                                                           ;
;   5.093 ;   0.086  ; RR ; RE   ; 1      ; C2_X75_Y326_N0_I25                         ; C2 interconnect             ; V2                                                                                                                                                                                           ;
;   5.175 ;   0.082  ; RR ; RE   ; 1      ; C2_X75_Y328_N0_I25                         ; C2 interconnect             ; V2                                                                                                                                                                                           ;
;   5.263 ;   0.088  ; RR ; RE   ; 1      ; R4_X72_Y330_N0_I58                         ; R4 interconnect             ; H4                                                                                                                                                                                           ;
;   5.398 ;   0.135  ; RR ; RE   ; 1      ; R4_X68_Y330_N0_I50                         ; R4 interconnect             ; H4                                                                                                                                                                                           ;
;   5.398 ;   0.000  ; RR ; RE   ; 1      ; R24_C16_INTERCONNECT_DRIVER_X67_Y330_N0_I3 ; R24/C16 interconnect driver ; WIRE_MUX                                                                                                                                                                                     ;
;   5.592 ;   0.194  ; RR ; RE   ; 1      ; C16_X67_Y330_N0_I26                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   5.732 ;   0.140  ; RR ; RE   ; 1      ; C16_X67_Y346_N0_I26                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   5.732 ;   0.000  ; RR ; RE   ; 1      ; R24_C16_INTERCONNECT_DRIVER_X67_Y354_N0_I2 ; R24/C16 interconnect driver ; WIRE_MUX                                                                                                                                                                                     ;
;   5.929 ;   0.197  ; RR ; RE   ; 1      ; C16_X67_Y354_N0_I26                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   6.065 ;   0.136  ; RR ; RE   ; 1      ; C4_X67_Y362_N0_I0                          ; C4 interconnect             ; V4                                                                                                                                                                                           ;
;   6.208 ;   0.143  ; RR ; RE   ; 2      ; LOCAL_INTERCONNECT_X68_Y366_N0_I46         ; Block interconnect          ; LAB_LINE                                                                                                                                                                                     ;
;   6.295 ;   0.087  ; RR ; RE   ; 1      ; LAB_RE_X68_Y366_N0_I13                     ; LAB_RE                      ; leimc1[1]                                                                                                                                                                                    ;
;   6.294 ;   -0.001 ;    ; IC   ; 1      ; LABCELL_X68_Y366_N9                        ; Combinational cell          ; fpga_top|inst_green_bs|lm_pipe[1].local_mem_avmm_bridge|ddr_avmm_bridge|wr_writedata[0]~138|datac                                                                                            ;
;   6.372 ;   0.078  ; RR ; CELL ; 1      ; LABCELL_X68_Y366_N9                        ; Combinational cell          ; fpga_top|inst_green_bs|lm_pipe[1].local_mem_avmm_bridge|ddr_avmm_bridge|wr_writedata[0]~138|combout                                                                                          ;
;   6.372 ;   0.000  ; RR ; CELL ; 1      ; FF_X68_Y366_N11                            ; ALM Register                ; fpga_top|inst_green_bs|lm_pipe[1].local_mem_avmm_bridge|ddr_avmm_bridge|cmd_writedata[1][138]|d                                                                                              ;
;   6.372 ;   0.000  ; RR ; CELL ; 1      ; FF_X68_Y366_N11                            ; ALM Register                ; fpga_top|inst_green_bs|lm_pipe[1].local_mem_avmm_bridge|ddr_avmm_bridge|cmd_writedata[1][138]                                                                                                ;
+---------+----------+----+------+--------+--------------------------------------------+-----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Data Required Path                                                                                                                                                       ;
+---------+----------+----+------+--------+-----------------+--------------+-----------------------------------------------------------------------------------------------+
; Total   ; Incr     ; RF ; Type ; Fanout ; Location        ; Element Type ; Element                                                                                       ;
+---------+----------+----+------+--------+-----------------+--------------+-----------------------------------------------------------------------------------------------+
; 3.440   ; 3.440    ;    ;      ;        ;                 ;              ; latch edge time                                                                               ;
; 6.204   ; 2.764    ;    ;      ;        ;                 ;              ; clock path                                                                                    ;
;   5.571 ;   2.131  ; R  ;      ;        ;                 ;              ; clock network delay                                                                           ;
;   6.236 ;   0.665  ;    ;      ;        ;                 ;              ; clock pessimism removed                                                                       ;
;   6.204 ;   -0.032 ;    ;      ;        ;                 ;              ; advanced clock effects                                                                        ;
; 6.174   ; -0.030   ;    ;      ;        ;                 ;              ; clock uncertainty                                                                             ;
; 6.305   ; 0.131    ;    ; uTsu ; 1      ; FF_X68_Y366_N11 ; ALM Register ; fpga_top|inst_green_bs|lm_pipe[1].local_mem_avmm_bridge|ddr_avmm_bridge|cmd_writedata[1][138] ;
+---------+----------+----+------+--------+-----------------+--------------+-----------------------------------------------------------------------------------------------+
llandis commented 4 years ago

These "shouldn't" come up. However worst case is worst process voltage temperature and the cards run in a cooled environment with carefully regulated voltage so the chance of seeing worst case silicon process along with edge conditions for voltage and temperature for this negative slack to cause incorrect results are somewhat low but not impossible. We'll look into it. Thanks for bringing this to our attention. Kind Regards Larry

sneharaogr commented 4 years ago

@llandis

Hi Larry

Thanks for your prompt reply. Look forward to your response re the cause of the problem.

Meanwhile, could you please let me know if there is an "official" way of doing things (eg: specific versions of Quartus and OPAE to be used together) or perhaps a restricted subset of corner cases to timing analyze so that the Intel supplied design compiles without any timing violations.

Regards, Sneha