Closed 65a closed 5 months ago
Thanks to @johnnylinwiwynn I was able to boot SeaBIOS, Linux, and u-boot. I didn't try grub again. Going over the configs carefully, I changed to XAPIC mode, enabled VPD FMAP, and properly configured the CXL. This boots fine, however option ROMs hang and do not work. I suspect this is because the legacy 8254 timer is clock gated, as older FSPs had a special config to keep this on, and Option ROMs appear to require it.
Hi 65a, I have the same problem when porting coreboot on our board. Some questions needs your help. Would you please share the detail configurations with me ?
It wasn't XAPIC, though in make menuconfig
you should adjust that setting. Instead, in the security section of coreboot config, set it to clear memory on every boot. You can usually boot without VPD FMAP keys set, but digging in the code will show you the options. For CXL, I don't use it, configuring any value is fine: more important to ensure the IOUs are configured appropriately for PCIe devices. Use the FSPs associated with this repo, include files from coreboot + FSP repo. Good luck, if you are from MITAC, I did get my Tyan board booting, as well as a Gigabyte, reliably.
Hi 65a, Thanks your comments. Yes, I am from MiTAC. We got our board booting with the workaround on the link https://review.coreboot.org/c/coreboot/+/82705 yesterday. The paging function of latest EGS FSP binary should be disabled to linux payload. Did you patch this workaround into your coreboot source tree ?
I'm trying to port the Tyan S5652 board to Coreboot. Using a gpio dump from inteltool, I have the running GPIO settings for the board. I started with Archercity CRB as a template, but updated the IIO configs to match my board. I immediately ran into some problems:
102 The headers are incomplete in the FSP git, and out-of-date in Coreboot
I hacked around 1 by merging the few headers in this repo back into Coreboot's old FSP headers, this sort of seems to work and stops triggering asserts. I never solved 2.
At this point, I was able to boot the board past romstage, and FspMemoryInit succeeds. In ramstage, I noticed new problems:
I suspect this all might be fallout from #102, but as far as I can tell the current FSP does not work in Coreboot, and most of the work seems to be happening by Intel insiders with access to development FSPs, headers and docs. Am I doing something wrong here?
The following payloads do not work at all:
I was able to get to a u-boot flat binary prompt with that payload, but since it cannot see through PCI bridges (apparently), I cannot boot with that either. I did not try EDK2 because I couldn't get VGA working.
Could Intel please try to build Archercity with only public files and confirm it actually works? Is there something obvious I am missing?