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Intel(R) Firmware Support Package (FSP)
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BayTrailFspBinPkg: FSP getting stuck when PCIe enabled in x4 #32

Closed amritpreetsingh91 closed 5 years ago

amritpreetsingh91 commented 5 years ago

Hi Whenever we enable PCIe in x1(All 4 ports in x1 configuration) the board boots well as expected and communication works. But as soon as we change the configuration in flash descriptor to PCIe x4(just port 1 in x4 configuration), the link gets up when the board boots but the FSP gets stuck. Is there a way we can debug this? OR the FSP supports only x1 configuration?

nate-desimone commented 5 years ago

Hi @amritpreetsingh91 the FSP for BayTrail was one of the very early implementations of FSP which nobody really used.

For coreboot, BayTrail used the old design of having "mrc.bin" without a spec defined interface. The "mrc.bin" binary is not re-distributable and Intel did not create or support it, so you will need to find a Bay Tail Chromebook firmware image and extract it to go this route.

For tianocore, Intel did support Bay Trail but in a different way. We distributed individual PEIM binaries instead of bundling them together in an FSP binary like newer Intel designs. Please see here:

https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/Vlv2SocBinPkg https://github.com/tianocore/edk2-platforms/tree/master/Platform/Intel/Vlv2TbltDevicePkg

I would recommend that you go with one of these options, as these were the methods used to get Bay Trail to product level quality before FSP became mature.

Bay Trail is a 7 year old chip, Intel does not actively develop firmware for it anymore so it won't match the much more consistent picture you see with newer Intel designs.