We have designed a custom board based on xeon D1559 processor. We used on board DDR4 memory chip of 8Gb with Part Number: MT40A512M16LY-062E ( https://www.micron.com/products/dram/ddr4-sdram/part-catalog/mt40a512m16ly-062e )
The memory per channnel is 4GB (1GB * 4 chips).
We prepared the SPD binary and provided it as memory down configuration. We are using the Grangeville fsp package (BDXDE_FSP_MR_002_RC5_20161115).
While the system boots up, the memory test failed. Our memory is in 512x16 configuration but we assume that the current code tests memory in x8 configuration. I have attached the debug log for reference.
Please let us know the area in which we can debug more in MRC or in SPD to resolve this issue.
Thanks in advance,
Omkar
DebugLog.txt
We have designed a custom board based on xeon D1559 processor. We used on board DDR4 memory chip of 8Gb with Part Number: MT40A512M16LY-062E ( https://www.micron.com/products/dram/ddr4-sdram/part-catalog/mt40a512m16ly-062e ) The memory per channnel is 4GB (1GB * 4 chips). We prepared the SPD binary and provided it as memory down configuration. We are using the Grangeville fsp package (BDXDE_FSP_MR_002_RC5_20161115). While the system boots up, the memory test failed. Our memory is in 512x16 configuration but we assume that the current code tests memory in x8 configuration. I have attached the debug log for reference. Please let us know the area in which we can debug more in MRC or in SPD to resolve this issue. Thanks in advance, Omkar DebugLog.txt