Enabling PcieRpHotPlug (or rather leaving it enabled) causes inconsistent MPS settings in the respective RPs:
DCAP Max Payload Size Supported will be cleared to 0 (128B)
DCTL Max Payload Size will be set to 1 (256B)
Whether or not the DCAP change is intentional is impossible to say. As usual there is no documentation about FSP. It's also possible that DCAP is written by accident (it's RW/O).
That DCTL is written at all is another issue.
Please issue a fixed binary or release the code to the public so we can work on a proper implementation (which would be much less expensive for Intel's hardware customers that are currently forced into beta testing your software).
Enabling
PcieRpHotPlug(or rather leaving it enabled) causes inconsistent MPS settings in the respective RPs:Whether or not the DCAP change is intentional is impossible to say. As usual there is no documentation about FSP. It's also possible that DCAP is written by accident (it's RW/O). That DCTL is written at all is another issue.
Please issue a fixed binary or release the code to the public so we can work on a proper implementation (which would be much less expensive for Intel's hardware customers that are currently forced into beta testing your software).