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intel / intel-cmt-cat

User space software for Intel(R) Resource Director Technology
http://www.intel.com/content/www/us/en/architecture-and-technology/resource-director-technology.html
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Cache allocation failed #135

Closed jackwangPKU closed 4 years ago

jackwangPKU commented 4 years ago

My machine is xeon silver4110(Intel(R) Xeon(R) Silver 4110 CPU @ 2.10GHz) with a 11-way LLC. Something wrong about LLC allocation happened on my machine when I used pqos. First, I wanna set COS0 to 0x400 using the option '-e' but the result of the option '-s' is 0x600, that is, pqos cannot set to 0x400(I have tried other cores, and the result is the same). Second, although I assign only one way to every core, the result shows some cores can sometimes occuppany more than one way, that is, the limitation doesn't work perfectly. So I wonder whether pqos can allocate LLC without any error and whether pqos can monitor LLC occupancy accurately. If I use pqos by mistake, please tell me directly. Thanks.

kmabbasi commented 4 years ago

Hi Jack,

  1. The CBM bits used by other entities are described as a "contention bit-mask" which is shown in the pqos logs Example: $ pqos -sv ... INFO: L3 CAT details: CDP support=1, CDP on=0, #COS=16, #ways=11, ways contention bit-mask 0x600 ... Setting one of these bits will always result in both bits being set. If you require to set a single way for a specified CLOS, you will have to use bits outside the contention bit-mask. Please refer to Intel SDM vol 3b Chapter 17 (Figure 17-32).

  2. Similar issue has already been discussed here https://github.com/intel/intel-cmt-cat/issues/134

Thanks, Khawar

kmabbasi commented 4 years ago

Hi Jack,

We haven't heard anything back from you. We are considering this issue has been resolve. Therefore, closing it now.

Thanks, Khawar