tkanteck
commented
2 years ago CAT detection path first it looks for CPUID CAT support (not found), then it looks for product brand string match (no match) and then, in the last step, it tries to poke CAT registers (seems to work). For all failed checks and failed register pokes you may see warning messages.
aleksinx
I am using Intel(R) Xeon(R) CPU E3-1240 v5 @ 3.50GHz processor and tried following command: pqos -sV
The output of the command is below:
NOTE: Mixed use of MSR and kernel interfaces to manage CAT or CMT & MBM may lead to unexpected behavior. INFO: CACHE: type 1, level 1, max id sharing this cache 2 (1 bits) DEBUG: CACHE: not inclusive, direct mapped, 8 way(s), 64 set(s), line size 64, 1 partition(s) INFO: CACHE: type 2, level 1, max id sharing this cache 2 (1 bits) DEBUG: CACHE: not inclusive, direct mapped, 8 way(s), 64 set(s), line size 64, 1 partition(s) INFO: CACHE: type 3, level 2, max id sharing this cache 2 (1 bits) DEBUG: CACHE: not inclusive, direct mapped, 4 way(s), 1024 set(s), line size 64, 1 partition(s) INFO: CACHE: type 3, level 3, max id sharing this cache 16 (4 bits) DEBUG: CACHE: inclusive, complex cache indexing, 16 way(s), 8192 set(s), line size 64, 1 partition(s) DEBUG: Detected core 0, socket 0, L2 ID 0, L3 ID 0, APICID 0 DEBUG: Detected core 1, socket 0, L2 ID 1, L3 ID 0, APICID 2 DEBUG: Detected core 2, socket 0, L2 ID 2, L3 ID 0, APICID 4 DEBUG: Detected core 3, socket 0, L2 ID 3, L3 ID 0, APICID 6 DEBUG: Detected core 4, socket 0, L2 ID 0, L3 ID 0, APICID 1 DEBUG: Detected core 5, socket 0, L2 ID 1, L3 ID 0, APICID 3 DEBUG: Detected core 6, socket 0, L2 ID 2, L3 ID 0, APICID 5 DEBUG: Detected core 7, socket 0, L2 ID 3, L3 ID 0, APICID 7 WARN: CPUID.0x7.0: Monitoring capability not supported! INFO: Monitoring capability not detected INFO: CPUID.0x7.0: L3 CAT not detected. Checking brand string... DEBUG: CPU brand string 'Intel(R) Xeon(R) CPU E3-1240 v5 @ 3.50GHz' WARN: Cache allocation not supported on model name 'Intel(R) Xeon(R) CPU E3-1240 v5 @ 3.50GHz'! ERROR: RDMSR failed for reg[0xc94] on lcore 0 INFO: L3CA capability detected INFO: L3 CAT details: CDP support=0, CDP on=0, #COS=4, #ways=16, ways contention bit-mask 0x0 INFO: L3 CAT details: cache size 8388608 bytes, way size 524288 bytes INFO: CPUID.0x7.0: L2 CAT not supported INFO: L2CA capability not detected INFO: CPUID.0x7.0: MBA not supported INFO: MBA capability not detected DEBUG: allocation init OK DEBUG: monitoring init aborted: feature not present L3CA COS definitions for Socket 0: L3CA COS0 => MASK 0xffff L3CA COS1 => MASK 0xffff L3CA COS2 => MASK 0xffff L3CA COS3 => MASK 0xffff Core information for socket 0: Core 0, L2ID 0, L3ID 0 => COS0 Core 1, L2ID 1, L3ID 0 => COS0 Core 2, L2ID 2, L3ID 0 => COS0 Core 3, L2ID 3, L3ID 0 => COS0 Core 4, L2ID 0, L3ID 0 => COS0 Core 5, L2ID 1, L3ID 0 => COS0 Core 6, L2ID 2, L3ID 0 => COS0 Core 7, L2ID 3, L3ID 0 => COS0`
Here it says WARN: Cache allocation not supported on model name 'Intel(R) Xeon(R) CPU E3-1240 v5 @ 3.50GHz'! But later it says INFO: L3CA capability detected. and then shows number of CLOS and ways etc. What do they mean? If it supports CAT on L3 then why that warning is given?