intel / intel-cmt-cat

User space software for Intel(R) Resource Director Technology
http://www.intel.com/content/www/us/en/architecture-and-technology/resource-director-technology.html
Other
685 stars 180 forks source link

How to modify the number of cache ways #229

Closed Biyi-lab closed 1 year ago

Biyi-lab commented 1 year ago

Q1: The default number of cache ways is 11, how can I modify it to achieve finer-grained LLC control? Q2: Is the minimum allocation magnitude of MBA 10%?

[root@root]# pqos -s
NOTE:  Mixed use of MSR and kernel interfaces to manage
       CAT or CMT & MBM may lead to unexpected behavior.
L3CA/MBA COS definitions for Socket 0:
    L3CA COS0 => MASK 0x7ff
    L3CA COS1 => MASK 0x3
    L3CA COS2 => MASK 0x7ff
    L3CA COS3 => MASK 0x7ff
    L3CA COS4 => MASK 0x7ff
    L3CA COS5 => MASK 0x7ff
    L3CA COS6 => MASK 0x7ff
    L3CA COS7 => MASK 0x7ff
    MBA COS0 => 100% available ...

[root@root]# pqos -s -v
NOTE:  Mixed use of MSR and kernel interfaces to manage
       CAT or CMT & MBM may lead to unexpected behavior.
INFO: Requested interface: AUTO
INFO: resctrl detected
INFO: Selected interface: OS
INFO: CACHE: type 1, level 1, max id sharing this cache 2 (1 bits)
INFO: CACHE: type 2, level 1, max id sharing this cache 2 (1 bits)
INFO: CACHE: type 3, level 2, max id sharing this cache 2 (1 bits)
INFO: CACHE: type 3, level 3, max id sharing this cache 64 (6 bits)
INFO: resctrl detected
INFO: Monitoring capability detected
INFO: L3CA capability detected
INFO: L3 CAT details: CDP support=1, CDP on=0, #COS=8, #ways=11, ways contention bit-mask 0x600
INFO: L3 CAT details: cache size 34603008 bytes, way size 3145728 bytes
INFO: L2CA capability not detected
INFO: MBA capability detected
INFO: MBA details: #COS=8, linear, max=90, step=10
INFO: OS support for MBA CTRL unknown

Thanks!

aleksinx commented 1 year ago

Q1. You can modify number of cache ways associated with COS using pqos -e command Q2. Yes, currently for all available hardware min MBA throttling is 10%