A question about the USE of Highest Way in l3_cat

[Zctoylm0927]

Hi, recently I'm trying intel-cmt-cat to test whether the isolation of LLC will make a difference to the performance.

When I set COS0 on socket0: sudo pqos -e "llc@0:0=0x400;" It shows:

NOTE: Mixed use of MSR and kernel interfaces to manage CAT or CMT & MBM may lead to unexpected behavior. SOCKET 0 L3CA COS0 => MASK 0x400 Allocation configuration altered.

But after that I check the config by: sudo pqos -s It shows:

$ sudo pqos -s NOTE: Mixed use of MSR and kernel interfaces to manage CAT or CMT & MBM may lead to unexpected behavior. L3CA/MBA COS definitions for Socket 0: L3CA COS0 => MASK 0x600 L3CA COS1 => MASK 0x7ff L3CA COS2 => MASK 0x7ff L3CA COS3 => MASK 0x7ff L3CA COS4 => MASK 0x7ff L3CA COS5 => MASK 0x7ff L3CA COS6 => MASK 0x7ff L3CA COS7 => MASK 0x7ff L3CA COS8 => MASK 0x7ff L3CA COS9 => MASK 0x7ff L3CA COS10 => MASK 0x7ff L3CA COS11 => MASK 0x7ff L3CA COS12 => MASK 0x7ff L3CA COS13 => MASK 0x7ff L3CA COS14 => MASK 0x7ff L3CA COS15 => MASK 0x7ff MBA COS0 => 100% available MBA COS1 => 100% available MBA COS2 => 100% available MBA COS3 => 100% available MBA COS4 => 100% available MBA COS5 => 100% available MBA COS6 => 100% available MBA COS7 => 100% available L3CA/MBA COS definitions for Socket 1: L3CA COS0 => MASK 0x7ff L3CA COS1 => MASK 0x7ff L3CA COS2 => MASK 0x7ff L3CA COS3 => MASK 0x7ff L3CA COS4 => MASK 0x7ff L3CA COS5 => MASK 0x7ff L3CA COS6 => MASK 0x7ff L3CA COS7 => MASK 0x7ff L3CA COS8 => MASK 0x7ff L3CA COS9 => MASK 0x7ff L3CA COS10 => MASK 0x7ff L3CA COS11 => MASK 0x7ff L3CA COS12 => MASK 0x7ff L3CA COS13 => MASK 0x7ff L3CA COS14 => MASK 0x7ff L3CA COS15 => MASK 0x7ff MBA COS0 => 100% available MBA COS1 => 100% available MBA COS2 => 100% available MBA COS3 => 100% available MBA COS4 => 100% available MBA COS5 => 100% available MBA COS6 => 100% available MBA COS7 => 100% available Core information for socket 0: Core 0, L2ID 0, L3ID 0 => COS0, RMID0 Core 2, L2ID 5, L3ID 0 => COS0, RMID0 Core 4, L2ID 1, L3ID 0 => COS0, RMID0 Core 6, L2ID 4, L3ID 0 => COS0, RMID0 Core 8, L2ID 2, L3ID 0 => COS0, RMID0 Core 10, L2ID 3, L3ID 0 => COS0, RMID0 Core information for socket 1: Core 1, L2ID 8, L3ID 1 => COS0, RMID0 Core 3, L2ID 13, L3ID 1 => COS0, RMID0 Core 5, L2ID 9, L3ID 1 => COS0, RMID0 Core 7, L2ID 12, L3ID 1 => COS0, RMID0 Core 9, L2ID 10, L3ID 1 => COS0, RMID0 Core 11, L2ID 11, L3ID 1 => COS0, RMID0

The L3CA COS0 turns to 0x600 instead of 0x400. It seems that I can't set the highest way alone. Is this a special design for CAT?

Looking forward to your reply. Thanks a lot!

[mdcornu]

Apologies for the delayed response. If you run pqos -Vs you will see a line similar to this: INFO: L3 CAT details: CDP support=1, CDP on=0, #COS=16, #ways=11, ways contention bit-mask 0x600

The "ways contention bit-mask" represents cache ways that are shared by other entities (e.g IO device such as PCIe, CXL, etc... ). When using CAT, those cache ways cannot be individually selected.

[Zctoylm0927]

Thanks for your reply.