What is shareable_bits in resctrl？Or what is "ways contention bit-mask" in pqos？

Here is my env：

Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                112
On-line CPU(s) list:   0-111
Thread(s) per core:    2
Core(s) per socket:    28
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Platinum 8280L CPU @ 2.70GHz
Stepping:              6
CPU MHz:               2700.000
BogoMIPS:              5400.00
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              39424K
NUMA node0 CPU(s):     0-27,56-83
NUMA node1 CPU(s):     28-55,84-111

[root@localhost home]# pqos -v
NOTE:  Mixed use of MSR and kernel interfaces to manage
       CAT or CMT & MBM may lead to unexpected behavior.
INFO: CACHE: type 1, level 1, max id sharing this cache 2 (1 bits)
INFO: CACHE: type 2, level 1, max id sharing this cache 2 (1 bits)
INFO: CACHE: type 3, level 2, max id sharing this cache 2 (1 bits)
INFO: CACHE: type 3, level 3, max id sharing this cache 64 (6 bits)
INFO: Monitoring capability detected
INFO: CPUID.0x7.0: L3 CAT supported
INFO: L3 CDP is disabled
INFO: L3CA capability detected
INFO: L3 CAT details: CDP support=1, CDP on=0, #COS=16, #ways=11, ways contention bit-mask 0x600
INFO: L3 CAT details: cache size 40370176 bytes, way size 3670016 bytes
INFO: CPUID 0x10.0: L2 CAT not supported!
INFO: L2CA capability not detected
INFO: MBA capability detected
INFO: MBA details: #COS=8, linear, max=90, step=10

At first，I use resctrl

echo "L3:0=3ff;1=3ff" > /sys/fs/resctrl/schemata
echo "L3:0=400;1=400" > /sys/fs/resctrl/COS1/schemata

but the core in COS1 works like using 2way， and

cat info/L3/shareable_bits
600

https://www.kernel.org/doc/html/v5.11/x86/resctrl.html “shareable_bits”: Bitmask of shareable resource with other executing entities (e.g. I/O). User can use this when setting up exclusive cache partitions. Note that some platforms support devices that have their own settings for cache use which can over-ride these bits. and
cat llc_occupancy while running my task，is about 7MiB(eq to 2way).

Recently，I use pqos

[root@localhost home]# pqos -R
NOTE:  Mixed use of MSR and kernel interfaces to manage
       CAT or CMT & MBM may lead to unexpected behavior.
Allocation reset successful
[root@localhost home]# pqos -e 'llc:0=0x400'
NOTE:  Mixed use of MSR and kernel interfaces to manage
       CAT or CMT & MBM may lead to unexpected behavior.
SOCKET 0 L3CA COS0 => MASK 0x400
SOCKET 1 L3CA COS0 => MASK 0x400
Allocation configuration altered.
[root@localhost home]# pqos -s
NOTE:  Mixed use of MSR and kernel interfaces to manage
       CAT or CMT & MBM may lead to unexpected behavior.
L3CA/MBA COS definitions for Socket 0:
    L3CA COS0 => MASK 0x600
    L3CA COS1 => MASK 0x7ff
    L3CA COS2 => MASK 0x7ff

MASK "0x400" changes to "0x600"

[root@localhost home]# pqos -s -v
NOTE:  Mixed use of MSR and kernel interfaces to manage
       CAT or CMT & MBM may lead to unexpected behavior.
INFO: CACHE: type 1, level 1, max id sharing this cache 2 (1 bits)
INFO: CACHE: type 2, level 1, max id sharing this cache 2 (1 bits)
INFO: CACHE: type 3, level 2, max id sharing this cache 2 (1 bits)
INFO: CACHE: type 3, level 3, max id sharing this cache 64 (6 bits)
INFO: Monitoring capability detected
INFO: CPUID.0x7.0: L3 CAT supported
INFO: L3 CDP is disabled
INFO: L3CA capability detected
INFO: L3 CAT details: CDP support=1, CDP on=0, #COS=16, #ways=11, ways contention bit-mask 0x600
INFO: L3 CAT details: cache size 40370176 bytes, way size 3670016 bytes
INFO: CPUID 0x10.0: L2 CAT not supported!
INFO: L2CA capability not detected
INFO: MBA capability detected
INFO: MBA details: #COS=8, linear, max=90, step=10

intel / intel-cmt-cat

What is shareable_bits in resctrl？Or what is "ways contention bit-mask" in pqos？ #252