misspellings - Githubissues

the Debian tool Lintian flags various common misspellings in the binaries:
occurrences of the misspellings in 1.0.10183 source:
Didnt => Didn't
IGC/Compiler/CISACodeGen/DebugInfoData.hpp:71:                IGC_ASSERT_MESSAGE(false, "Didnt find VISA dcl id");
visa/VarSplit.cpp:69:        MUST_BE_TRUE(found, "Didnt find child dcl");
visa/VarSplit.cpp:81:                MUST_BE_TRUE(inst->isSplitIntrinsic(), "Didnt expect new non-split intrinsic instruction");
visa/VarSplit.cpp:556:            MUST_BE_TRUE(dcl, "Didnt find split dcl");
visa/Rematerialization.cpp:1007:                MUST_BE_TRUE(ops != operations.end(), "Didnt find record in map");

Dont => Don't
visa/Passes/LVN.cpp:403:            // => Dont replace V1<16;8,2> with V0<8;8,1> because it would make
visa/VarSplit.cpp:398:            // Dont emit split if all uses are closeby
visa/FlowGraph.cpp:1226:            // Dont insert EOT send for FC composable kernels
visa/G4_IR.cpp:6255:        // Dont do float conversions
visa/GraphColor.cpp:3574:        MUST_BE_TRUE(false, "Dont know how to handle this type of operand");
visa/GraphColor.cpp:8757:        // Dont run analysis for addressed opnds.
visa/GraphColor.cpp:10447:                    // Dont modify program if reRA pass spills
visa/Rematerialization.cpp:776:                    // Dont remat if sampler def is outside loop and use inside loop
visa/SpillCleanup.cpp:390:            // Dont coalesce patterns like
visa/SpillManagerGMRF.cpp:4889:        // a0 is a caller save register. Dont save/restore it if it is used in callee save/restore sequence or

Funtions => Functions
IGC/BiFModule/Languages/OpenCL/opencl_cth_released.h:3236:  // Write Image Funtions

Messsages => Messages
visa/BuildCISAIRImpl.cpp:1812:        std::cerr << "[vISA Finalizer Messsages]\n" << criticalMsg.str();

Ouput => Output
IGC/common/IntrinsicAnnotator.cpp:28:            OS << "; Ouput: " << out << "\n";

Shouldnt => Shouldn't
visa/VarSplit.cpp:86:                MUST_BE_TRUE(!inst->getSrc(0)->getTopDcl()->getAddressed(), "Shouldnt split indirectly addressed variable");

Unknow => Unknown
IGC/Metrics/IGCMetricImpl.cpp:248:                    IGC_ASSERT_MESSAGE(false, "Unknow Function type");
visa/BinaryEncodingIGA.cpp:491:        ASSERT_USER(false, "Unknow SFID generated from vISA");

auxilary => auxiliary
visa/iga/IGALibrary/Backend/Messages/MessageDecoderOther.cpp:746:            desc = "sample load mcs auxilary data";

continous => continuous
visa/GraphColor.cpp:9135:            //Since the whole range is inserted first, all the ranges should be continous.
visa/GraphColor.cpp:9136:            ASSERT_USER((*it)->leftBound - range->rightBound == 1, "none continous spliting happened\n");

extenstion => extension
IGC/Compiler/Optimizer/OpenCLPasses/ExtenstionFuncs/ExtensionArgAnalysis.cpp:22:#define PASS_DESCRIPTION "Analyzes extenstion functions arguments"
visa/G4_IR.cpp:1683:            // Treat ABS as zero-extenstion.
visa/G4_IR.cpp:1702:    // Treat ABS as zero-extenstion.

interger => integer
visa/IsaVerification.cpp:1699:            "%s only supports interger D/W type", ISA_Inst_Table[opcode].str);

intruction => instruction
3d/common/iStdLib/CpuUtil.h:39:    Returns the highest level of IA32 intruction extensions supported by the CPU
IGC/Compiler/LegalizationPass.cpp:631:    // This is the pass that folds 2x Float into a Double replacing the bitcast intruction
IGC/VectorCompiler/include/vc/GenXOpts/GenXAnalysis.h:55:/// Given a GenX related intruction, see if we can fold the
IGC/VectorCompiler/lib/GenXCodeGen/GenX.td:83:                                       "enable support for native add64 intruction">;
IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp:162:        (Twine("CISA builder failed for intruction <") + Str + ">: " + Desc)
IGC/VectorCompiler/lib/GenXCodeGen/GenXDepressurizer.cpp:849:    // v1  := twoaddr(v0); // two-addr intruction.
IGC/VectorCompiler/lib/GenXOpts/CMAnalysis/ConstantFoldingGenX.cpp:273:    LLVM_DEBUG(dbgs() << "Successfully constant folded intruction to "
visa/iga/IGALibrary/api/kv.h:369: * This function returns if intruction has destination.
visa/IsaVerification.cpp:2219:                default: REPORT_INSTRUCTION(options,false, "cntrl for CISA SAMPLER AVS intruction should be a "
visa/IsaVerification.cpp:2238:                default: REPORT_INSTRUCTION(options,false, "execMode for CISA SAMPLER AVS intruction should "
visa/G4_IR.cpp:318:        "setOpcode would change the intruction class, which is illegal.");
visa/G4_IR.cpp:4937:                we need to set leftBound for pseudo intruction
visa/G4_IR.cpp:6503:                we need to set leftBound for pseudo intruction
visa/Optimizer.cpp:9326:        //    add    dst     -dst    call_target   // at this intruction dst is the ip value

intructions => instructions
IGC/Compiler/Optimizer/PreCompiledFuncImport.cpp:171:// This function scans intructions before emulation. It converts double-related
IGC/VectorCompiler/lib/GenXCodeGen/GenXCategory.cpp:728:  // are used in send intructions.
visa/iga/IGAExe/iga_main.cpp:505:        "enables load/store pseudo intructions where possible",

mutiple => multiple
visa/Passes/MergeScalars.cpp:46:    MUST_BE_TRUE((offset % eltBytes) == 0, "Offset shoule be mutiple of element size");

regsiter => register
IGC/common/igc_flags.h:57:DECLARE_IGC_REGKEY(DWORD,ReservedRegisterNum,           0,     "Reserve regsiter number for spill cost testing.", false)
visa/LocalScheduler/LocalScheduler_G4IR.cpp:3103:                        //The same regsiter is reused in both SIMD8 instructions
visa/LocalScheduler/LocalScheduler_G4IR.cpp:3124:    else    //For SIMD16 and SIMD32, if the GRF1 of src1 or src2 of inst 1 is GRF regsiter
visa/BuildIRImpl.cpp:143:        MUST_BE_TRUE(false, "INPUT payload execeeds the regsiter number");
visa/GraphColor.cpp:324:    //In case src1 and src2 share same declare, i.e. use same regsiter
visa/GraphColor.cpp:689:    //In case (src0) src1 and src2 use same declare, i.e. use same regsiter
visa/GraphColor.cpp:840:    //In case (src0) src1 and src2 use same declare, i.e. use same regsiter
visa/GraphColor.h:1375:        unsigned   linearizedStart; //linearized start regsiter address
visa/GraphColor.h:1376:        unsigned   linearizedEnd;   //linearized end regsiter address
visa/HWConformity.cpp:7031:            // check if the opnd has pre-assigned physical regsiter
visa/HWConformity.cpp:7064:            // check if the opnd has pre-assigned physical regsiter

shoule => should
visa/Passes/MergeScalars.cpp:46:    MUST_BE_TRUE((offset % eltBytes) == 0, "Offset shoule be mutiple of element size");

spliting => splitting
IGC/BiFModule/Implementation/barrier.cl:123:        // nothing will be emited but we need to prevent optimization spliting control flow
IGC/Compiler/CISACodeGen/CISABuilder.cpp:6586:                // two SIMD8 data payload by spliting the original simd16 data payload.
IGC/Compiler/CISACodeGen/EmitVISAPass.cpp:16359:        // CISABuilder does split if there is any spliting.
IGC/Compiler/CISACodeGen/EmitVISAPass.cpp:16397:        // Only dst might need spliting.
IGC/Compiler/CISACodeGen/EmitVISAPass.cpp:16569:        // at most and dst's stride == 1, so it will not need spliting.
visa/G4_IR.cpp:863:// remove the faked def-instructions in def list, which is resulted from instruction spliting
visa/GraphColor.cpp:9136:            ASSERT_USER((*it)->leftBound - range->rightBound == 1, "none continous spliting happened\n");
visa/HWConformity.cpp:6176:                // No spliting needed for an inst whose execsize <= nativeES, as
visa/HWConformity.cpp:6692:            MUST_BE_TRUE(secondHalfOp, "Error in spliting instruction.");
visa/ReduceExecSize.cpp:135:// to avoid spliting of the MOV inserted in this stage.
visa/ReduceExecSize.cpp:701:    // to avoid instruction spliting. inserted MOVs may be split into multiple instructions.
visa/ReduceExecSize.cpp:707:        // perform spliting on new MOV instructions.
visa/ReduceExecSize.cpp:710:            // try to move 2-GRF src into 1GRF tmp to avoid spliting.
visa/ReduceExecSize.cpp:830:        // In some cases spliting the instruction generates the same number of instruction
visa/ReduceExecSize.cpp:847:    // they do not need spliting
visa/ReduceExecSize.cpp:849:    // sure only evenly spliting will happen to them.

unknow => unknown
IGC/Compiler/CISACodeGen/CShader.cpp:2730:    IGC_ASSERT_MESSAGE(0, "unknow SIMD constant expression");
visa/IsaVerification.cpp:1915:                         "All operands of logic instructions must be of integral type! opnd %d has unknow type %d",

vaild => valid
visa/IsaVerification.cpp:3995:            "S%d's number of elements(%d) is not vaild", i, header->getSampler(i)->num_elements);
BTW, what's the correct plural of the data type half? (I've excluded the occurrences of halfs from above list)
intel / intel-graphics-compiler

misspellings #229
