Closed Jean-Mick closed 6 years ago
Hello Jean-Mick,
Thanks for pointing it out. I looked into the code and the remaining AVX512 code (SHA1/SHA256/SHA512) requires AVX512F, AVX512BW and some instruction formats require AVX512VL. All of these AVX512 extensions are supported by latest Intel(R) Xeon(R) Scalable Processors.
I'll add these notes to README and assembly files. Let me keep this issue open until I do so.
Thanks, Tomasz
As part of the recent README update dfbb5800a26ef58dd709cc384cc8e711bca0105f, a note has been added about AVX512 extensions. See here https://github.com/intel/intel-ipsec-mb/blob/master/README#L124. If you find this information not sufficient or lacking some data then feel free to re-open this issue. Thanks
Hello, Could you add to README which AVX512 set is required by algo ? Only DES case is mentioned with AVX512F and AVX512BW.
Thanks