Open chengjunlu opened 2 months ago
@chengjunlu, @whitneywhtsang could you please file the ticket and share it's number with me offline.
@chengjunlu, @whitneywhtsang could you please file the ticket and share it's number with me offline.
Yes, we are still preparing the content for the ticket.
IGC team has confirmed that they are working on the task to support general 2D load interface thru the SPIRV Intel Block IO extension.
New 2D load variants are used in FP8 load. https://github.com/intel/intel-xpu-backend-for-triton/commit/5f088429c8aeb0082c262d812945c2b4e7b86233
llvm.genx.GenISA.LSC2DBlockRead.v32i8
New transpose 2D load variants are used in flash attention.
llvm.genx.GenISA.LSC2DBlockRead.v16i32
We are using the GENISA if it is not exist in OCL interface for now. Need to summary the new requirements and file JIRA to IGC to track.