Open ESI-SYD opened 1 week ago
@ESI-SYD what is the root cause for this issue? can you pin point it to a particular torch
operation?
@anmyachev to proceed further with analysis / triaging please create a minimal reproducer for the Triton kernel path.
@ESI-SYD what is the root cause for this issue? can you pin point it to a particular
torch
operation?
There are two main differences in benchmark time method change after applying the Draft
No sync submitting. https://github.com/intel/intel-xpu-backend-for-triton/blob/llvm-target/python/triton/testing.py#L214
Use the time stamp between two barriers which is not accurate. Previous detailed explanation by chengjun.
Triton
/XeTLA
keep same except for attention caused byXeTLA
attention absolute number degradedTriton
andXeTLA
softmax cases degraded, soTriton
/XeTLA
not changed.details: https://github.com/intel/intel-xpu-backend-for-triton/pull/1905#issuecomment-2320701513