Closed CuiYifeng closed 9 months ago
This is related to SPIR-V lowering path. Can you please recheck after migration to the llvm-target.
Will double check if this issue happens in LLVM path when E2E could run.
The llvm branch has reached parity with the spirv branch in terms of the UT pass rate. Closing the issue.
Issue Description
Intel-xpu-backend-for-triton
>
operator does not supporti1
but triton for CUDA can.Code Example
Please find example in attachment. maml_cuda.txt is triton code generated with Pytorch CUDA. The above triton code segment also appears in it. maml_xpu_to_cuda.txt is triton code generated with XPU backend. It works with Pytorch CUDA after replacing the header.
System Info