The MultiCycleDivider has the following bugs:
(1) Polarity of the readyIn output is flipped relative to what it should be.
(2) Unsigned cases of division involving very large operands (MSB=1) do not produce correct results and can even deadlock the unit.
This PR fixes these and adds tests for the exceptional cases moving forward.
Related Issue(s)
N/A
Testing
Added a new sequence for "evil" cases of division stressing large operands in both signed and unsigned. Fixed a bug in the testbench preventing testing of readyIn signal.
Backwards-compatibility
Is this a breaking change that will not be backwards-compatible? If yes, how so?
This change is backward compatible as the interface to the divider has not changed at all. Only the outputs for a given set of inputs have changed in certain cases.
Documentation
Does the change require any updates to documentation? If so, where? Are they included?
Documentation updated to address the case of signed division overflow which was also added as a test case and needs explicitly clarification on unit behavior.
Description & Motivation
The MultiCycleDivider has the following bugs: (1) Polarity of the readyIn output is flipped relative to what it should be. (2) Unsigned cases of division involving very large operands (MSB=1) do not produce correct results and can even deadlock the unit.
This PR fixes these and adds tests for the exceptional cases moving forward.
Related Issue(s)
N/A
Testing
Added a new sequence for "evil" cases of division stressing large operands in both signed and unsigned. Fixed a bug in the testbench preventing testing of readyIn signal.
Backwards-compatibility
This change is backward compatible as the interface to the divider has not changed at all. Only the outputs for a given set of inputs have changed in certain cases.
Documentation
Documentation updated to address the case of signed division overflow which was also added as a test case and needs explicitly clarification on unit behavior.