intel / rohd

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
https://intel.github.io/rohd-website
BSD 3-Clause "New" or "Revised" License
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A helper function to save generated System Verilog string as a file #239

Open quekyj opened 1 year ago

quekyj commented 1 year ago

Motivation

I'm wondering if we can have a helper function to save system Verilog module generateSynth() to a file. Its a pain to keep copy pasting the code below to keep track of system verilog code generated.

import 'dart:io';

final res = mod.generateSynth();
final out = File('output.txt').openWrite();
out. Write(res);

File('temp.sv').writeAsStringSync(myString);

I am thinking maybe someone who also beneficial to have the system verilog .sv file as well.

Desired solution

There are two ways I can think of.

First is update:

Second:

Alternatives considered

No response

Additional details

No response

mkorbel1 commented 1 year ago

Different cases to consider:

Each of these options might use a different Synthesizer

The API should be simple to use for all these cases for any Synthesizer.

Maybe something like this, where both options take Synthesizer as an option? generateSynth -> returns String, optionally additionally dumps to file with all modules in one file? generateSynthPerModule -> returns List<SynthResult>, optionally additionally dumps to a directory?