} else if (driver == null && receiver.value.isValid) {
assignments.add(_SynthAssignment(receiver.value, synthReceiver));
} else if (driver == null && !receiver.value.isFloating) {
// this is a signal that is *partially* invalid (e.g. 0b1z1x0)
assignments.add(_SynthAssignment(receiver.value, synthReceiver));
}
This appears to indicate that if a signal has no driver, yet has valid (or partially valid) values, then the generation of SystemVeriog will conclude that it must be a constant value. This means non-synthesizable signal deposition like put could affect the constant values present in generated outputs. The checks for constants need to be more significant, such as checking for Const, unassignable, etc.
To Reproduce
Make a design with an undriven signal which has a valid value deposited via put and check generated SystemVerilog of the design.
Expected behavior
An undriven signal remains undriven in generated outputs.
Actual behavior
An undriven signal, with a value deposited on it, becomes a constant value in generated outputs.
Describe the bug
Code like this exists in "systemverilog.dart":
This appears to indicate that if a signal has no driver, yet has valid (or partially valid) values, then the generation of SystemVeriog will conclude that it must be a constant value. This means non-synthesizable signal deposition like
putcould affect the constant values present in generated outputs. The checks for constants need to be more significant, such as checking forConst,unassignable, etc.To Reproduce
Make a design with an undriven signal which has a valid value deposited via
putand check generated SystemVerilog of the design.Expected behavior
An undriven signal remains undriven in generated outputs.
Actual behavior
An undriven signal, with a value deposited on it, becomes a constant value in generated outputs.
Additional: Dart SDK info
No response
Additional: pubspec.yaml
No response
Additional: Context
No response