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intel / rohd

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
https://intel.github.io/rohd-website
BSD 3-Clause "New" or "Revised" License
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Left-shift can cause width mismatch in generated SystemVerilog #298

Closed mkorbel1 closed 1 year ago

mkorbel1 commented 1 year ago

Describe the bug

The rules around left-shifting in SystemVerilog allow for the width of the result to be different than the width of the original value being shifted in some circumstances. This can hit lint violations or perhaps strange bugs and inconsistencies in generated verilog.

To Reproduce

Perform left-shift around other signals of various widths. There may be many combinations to explore.

Expected behavior

No response

Actual behavior

No response

Additional: Dart SDK info

No response

Additional: pubspec.yaml

No response

Additional: Context

No response

mkorbel1 commented 1 year ago

A similar thing can happen with adding (carry bit)