Add clog2 functionality - Githubissues

intel / rohd

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

https://intel.github.io/rohd-website

BSD 3-Clause "New" or "Revised" License

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Add clog2 functionality #337

Closed mkorbel1 closed 1 year ago

mkorbel1 commented 1 year ago

Motivation

In SystemVerilog, $clog2 is a useful function.

It would be nice to have a synthesizable Module and associated functions for generating hardware and SystemVerilog with $clog2

Desired solution

Create a new Module that generates $clog2 in output SystemVerilog and appropriately simulates in the ROHD simulator.
Add functions (probably to Logic) to automatically generate this module in a convenient API.

Alternatives considered

No response

Additional details

No response

mkorbel1 commented 1 year ago

Closed in #361