It's possible to generate outputs using a Synthesizer and SynthBuilder rather than through Module.generateSynth. However, the SynthBuilder does not check that Module.build is called, only generateSynth does. This can produce unexpected outputs (e.g. SystemVerilog with no submodules) without any helpful error message indicating why.
Related Issue(s)
Fix #246
Testing
Tested with module not built and catch exception.
Backwards-compatibility
Is this a breaking change that will not be backwards-compatible? If yes, how so?
Yes.
Documentation
Does the change require any updates to documentation? If so, where? Are they included?
Description & Motivation
It's possible to generate outputs using a Synthesizer and SynthBuilder rather than through Module.generateSynth. However, the SynthBuilder does not check that Module.build is called, only generateSynth does. This can produce unexpected outputs (e.g. SystemVerilog with no submodules) without any helpful error message indicating why.
Related Issue(s)
Fix #246
Testing
Tested with module not built and catch exception.
Backwards-compatibility
Yes.
Documentation
No. Just added validation and test.