FSM abstraction have issue on priority condition

[quekyj]

Describe the bug

In the current implementation of the FSM, the generated system Verilog used unique case. Hence, it will throw error when there more than one event occurred at same clock.

To Reproduce

1. Create FSM using ROHD abstraction
2. Use Simulator() to simulate more than one event that occurred at the same flops.

Expected behavior

No response

Actual behavior

Alternative 1: Create a priority FSM that allows user to give priority of which one to execute in the case of two events happened at the same time.

Additional: Dart SDK info

No response

Additional: pubspec.yaml

No response

Additional: Context

No response

[mkorbel1]

We should implement an ability to control different ConditionalTypes for FSM abstractions as well to support this type of use case.

There's two types of Case statement used in the FSM abstraction:

• The top-level one based on current state.
• The nested ones deciding on how to handle different events.

Perhaps the top-level one should always be unique? The nested ones definitely seem like having things like priority could be helpful. Perhaps we want the nested ones to be configurable on a per-state basis? Perhaps we want to have a configurable "default" type across states at the top-level of the state machine?