Adds both LogicStructure and LogicArray implementations to ROHD. See new documentation for details on API and usage.
It also adds a variety of bug fixes, both previously found and newly discovered.
Implements #36, the main issue for this PR.
Fixes #254, where non-synthesizable signal deposition could impact constant values on undriven signals.
Fixes #311, where signal width mismatch exceptions were poor.
Fixes a bug where indexing of constant values generated invalid SystemVerilog.
Fixes a bug where constants and LogicValues with negative 64-bit values would generate invalid SystemVerilog notation (with a - sign).
Adds ConditionalGroup, a single Conditional that accepts a collection of other Conditionals for grouping them together.
Adds LogicValue.of which accepts a dynamic input and tries its best to build what you're looking for. Adds LogicValue.ofIterable to replace the old LogicValue.of.
Adds a variety of new tests for various features that were previously under-tested.
Updates some typos in the README
Fixed the oven FSM example to not generate the oven_fsm.md file during tests.
Reorganized Logic and related content into a new signals directory.
Minor fix in the IterableRemovableQueue to make code more readable.
Modified SignalRedrivenException constructor to accept a list of signals instead of just a string.
Added a new LogicConstructionException type for failures in construction of a signal.
Added a new SignalWidthMismtachException type for failures in connecting two signals together, and updated PortWidthMismatchException.
Added a new LogicValueConstructionException type for failures when creating a LogicValue
Upgrades for getRange, swizzle, slice, etc. that remove unnecessary module creation when there are 0-width or only 1 element.
Added information in Logic related to LogicStructures and LogicArrays: isArrayMember, structureName, arrayIndex, parentStructure
Migraded index wrapping modification code into a separate reusable utility
Made some Lists non-growable for minor perf enhancement
Description & Motivation
Adds both
LogicStructure
andLogicArray
implementations to ROHD. See new documentation for details on API and usage.It also adds a variety of bug fixes, both previously found and newly discovered.
LogicValue
s with negative 64-bit values would generate invalid SystemVerilog notation (with a-
sign).ConditionalGroup
, a singleConditional
that accepts a collection of otherConditional
s for grouping them together.LogicValue.of
which accepts adynamic
input and tries its best to build what you're looking for. AddsLogicValue.ofIterable
to replace the oldLogicValue.of
.oven_fsm.md
file during tests.Logic
and related content into a newsignals
directory.IterableRemovableQueue
to make code more readable.SignalRedrivenException
constructor to accept a list of signals instead of just a string.LogicConstructionException
type for failures in construction of a signal.SignalWidthMismtachException
type for failures in connecting two signals together, and updatedPortWidthMismatchException
.LogicValueConstructionException
type for failures when creating aLogicValue
getRange
,swizzle
,slice
, etc. that remove unnecessary module creation when there are 0-width or only 1 element.Logic
related toLogicStructure
s andLogicArray
s:isArrayMember
,structureName
,arrayIndex
,parentStructure
List
s non-growable for minor perf enhancementException
s toError
s (and updated https://github.com/intel/rohd/issues/105)Also opened some new issues:
376 tracking completion of testing of SystemVerilog generated for unpacked arrays until bugs are fixed in SystemVerilog simulators.
377 tracking part-assign automation for
LogicArray
sLogicArray
support to ROHD CosimRelated Issue(s)
Fix #36 Fix #254 Fix #311
Testing
Extensive new tests written and existing tests upgraded.
Backwards-compatibility
Yes, a variety of small changes.
mulAssign
anddivAssign
APIs have changed slightly.ConditionalAssign
now returnConditional
(e.g.<
operator forLogic
).Documentation
Yes, added new docs in the user guide.